PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 441
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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28.1.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
W
W
Q1
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
STANDARD INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
=
=
10h
25h
literal ‘k’
ADD Literal to W
ADDLW
0 k 255
(W) + k W
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
1
1
ADDLW
Read
0000
Q2
0x15
k
1111
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
PIC18F46J50 FAMILY
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
ADDWF
0 f 255
d [0,1]
a [0,1]
(W) + (f) dest
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 28.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
ADDWF
Read
0010
Q2
17h
0C2h
0D9h
0C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
DS39931D-page 441
ffff
for details.
destination
Write to
Q4
ffff
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