LPC47M182-NR SMSC [SMSC Corporation], LPC47M182-NR Datasheet - Page 89
LPC47M182-NR
Manufacturer Part Number
LPC47M182-NR
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M182-NR.pdf
(223 pages)
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note
Note
SMSC LPC47M182
1
2
: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
: The High Speed bit is located in the Device Configuration Space.
BAUD RATE
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
DESIRED
115200
230400
460800
19200
38400
57600
134.5
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
GENERATE 16X CLOCK
DIVISOR USED TO
32770
32769
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
Table 6.30 - Baud Rates
DATASHEET
BETWEEN DESIRED AND ACTUAL
PERCENT ERROR DIFFERENCE
89
0.001
0.004
0.005
0.030
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
0.16
0.16
0.16
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-
1
SPEED BIT
HIGH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
2
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