MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 109

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

8.3.6 Programming the PLL
MC68HC908AP Family — Rev. 2.5
MOTOROLA
NOTE:
The following conditions apply when in manual mode:
The following procedure shows how to program the PLL.
The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
2. Choose a practical PLL reference frequency, f
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Software must wait a given time, t
The LOCK bit is disabled.
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
CPU interrupts from the CGM are disabled.
frequency, f
The relationship between f
equation:
where P is the power of two multiplier, and can be 0, 1, 2, or 3
reference clock divider, R. Typically, the reference is 32.768kHz
and R = 1.
Frequency errors to the PLL are corrected at a rate of f
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate.
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VCLKDES
ACQ
f
VCLK
(See
=
2
; and then solve for the other.
P
8.8 Acquisition/Lock Time
×
f
CGMPCLK
BUS
and f
=
AL
2
, after entering tracking mode
VCLK
P
BUSDES
×
Clock Generator Module (CGM)
4
×
is governed by the
f
BUS
, or the desired VCO
RCLK
Functional Description
, and the
RCLK
Data Sheet
/R. For
109