MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 351

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.3.7 Data Register Interlocking
17.3.8 Monotonicity
MC68HC908AP Family — Rev. 2.5
MOTOROLA
Left justification will place the eight most significant bits (MSB) in the
corresponding ADC data register high (ADRH). This may be useful if the
result is to be treated as an 8-bit result where the least significant two
bits, located in the ADC data register low (ADRL) can be ignored.
However, you must read ADRL after ADRH or else the interlocking will
prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC
data register high (ADRH) and the eight LSB bits in ADC data register
low (ADRL). This mode of operation typically is used when a 10-bit
unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one
exception. The MSB of the 10-bit result, AD9 located in ADRH is
complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed.
Finally, 8-bit truncation mode will place the eight MSBs in ADC data
register low (ADRL). The two LSBs are dropped. This mode of operation
is used when compatibility with 8-bit ADC designs are required. No
interlocking between ADRH and ADRL is present.
Reading ADRH in any 10-bit mode latches the contents of ADRL until
ADRL is read. Until ADRL is read all subsequent ADC results will be lost.
This register interlocking can also be reset by a write to the ADC status
and control register, or ADC clock control register. A power-on reset or
reset will also clear the interlocking. Note that an external conversion
request will not reset the lock.
The conversion process is monotonic and has no missing codes.
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
Analog-to-Digital Converter (ADC)
Functional Description
Data Sheet
351