HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 575
HD6412320
Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412320.pdf
(1302 pages)
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11.3
11.3.1
PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set
to 1. In this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating
conditions.
Table 11.3 PPG Operating Conditions
NDER
0
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before
the next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
Pulse output pin
Operation
Overview
0
1
0
1
DDR
Pin Function
Generic input port
Generic output port
Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
DDR
Q
Figure 11.2 PPG Output Operation
Normal output/inverted output
Section 11 Programmable Pulse Generator (PPG)
Q
NDER
PODR
Q
C
Output trigger signal
Rev.6.00 Sep. 27, 2007 Page 545 of 1268
D
Q
NDR
D
REJ09B0220-0600
Internal data bus
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