HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 241

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 6.2
ABWCR
ABWn
0
1
(n = 0 to 7)
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS) Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
ASTCR
ASTn
0
1
0
1
Bus Specifications for Each Area (Basic Bus Interface)
Wn2
⎯
0
1
⎯
0
1
WTCRA, WTCRB
Wn1
⎯
0
1
0
1
⎯
0
1
0
1
Wn0
⎯
0
1
0
1
0
1
0
1
⎯
0
1
0
1
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
Rev.7.00 Mar. 18, 2009 page 173 of 1136
Section 6 Bus Controller (BSC)
Access
States
2
3
2
3
REJ09B0109-0700
Program Wait
States
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7