HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 309

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.7.15
When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output
timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous
DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits
select whether or not burst access is to be performed. The establishment time for the read data can
be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.
(1) Output Timing of DACK or EDACK
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK
output goes low from the T
Figure 6.60 shows the DACK or EDACK output timing for the synchronous DRAM interface
when DDS = 1 or EDDS = 1.
DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM
Interface
c1
state.
Rev.7.00 Mar. 18, 2009 page 241 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700