HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 160

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
• CS6BWCR
Rev. 6.00 Jun. 12, 2007 Page 128 of 610
REJ09B0131-0600
Bit
31 to 21
20
19 to 13
12
11
Bit Name

BAS

SW1
SW0
Initial
Value
All 0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
1: Asserts the WEn (BEn) signal during the read/write
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WEn (BEn) assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(signal used as strobe) and asserts the RD/WR signal
during the write access cycle (signal used as status)
access cycle (used as status) and asserts the RD/WR
signal at the write timing (used as strobe)