AT25128A ATMEL [ATMEL Corporation], AT25128A Datasheet - Page 9

• Manufacturer Part Number: AT25128A
• Description: SPI Serial Extended Temperature EEPROMs
• Manufacturer: ATMEL [ATMEL Corporation]

AT25128A/256A
tion selected by the block write protection level. During an internal write cycle, all
commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code is transmitted via the SI line followed by the byte
address and the data (D7–D0) to be programmed (see Table 10). Programming will start
after the CS pin is brought high. The low-to-high transition of the CS pin must occur dur-
ing the SCK low time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a Read Status
Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the RDSR instruction is enabled during the write pro-
gramming cycle.
The AT25128A/256A is capable of a 64-byte page write operation. After each byte of
data is received, the six low-order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more than 64 bytes of data are
transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128A/256A is automatically returned to the write disable state at
the completion of a write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state when CS is brought high. A new CS falling
edge is required to reinitiate the serial communication.
Table 10. Address Key
Address
AT25128A
AT25256A
A
A
– A
A
– A
N
13
0
14
0
Don’t Care Bits
A
– A
A
15
14
15
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