NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 20
NAND08GW3C2A
Manufacturer Part Number
NAND08GW3C2A
Description
8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.NAND08GW3C2A.pdf
(58 pages)
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Command set
5
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Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
Program and Erase operations are imposed to maximize data security.
The commands are summarized in
Table 7.
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
Read
Random Data Output
Page Program
(sequential input default)
Multiplane Page Program
Random Data Input
Block Erase
Multiplane Block Erase
Reset
Read Electronic Signature
Read Status Register
input/output data are not shown.
Command
Commands
1
st
FFh
00h
05h
80h
80h
85h
60h
60h
90h
70h
cycle
Table 7:
Bus write operations
2
nd
D0h
Commands.
E0h
30h
10h
11h
60h
cycle
–
–
–
–
NAND08GW3C2A, NAND16GW3C2A
3
rd
D0h
81h
cycle
–
–
–
–
–
–
–
–
(1)
4
th
10h
cycle
–
–
–
–
–
–
–
–
–
during busy
Commands
accepted
Yes
Yes
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