HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet
HYB18M1G320BF
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HYB18M1G320BF Summary of contents
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... HYB18M1G320BF–7.5, HYE18M1G320BF–7.5, Revision History: 2007-03, Rev.1.00 Page Subjects (major changes since last revision) All Portfolio Change Previous Revision: Rev. 0.61, 2007-02 All Qimonda update Updates see Change List Rev.1.00, 2007-03 02022006-J7N7-GYFP HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM 2 Data Sheet ...
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Overview 1.1 Features • Low power DDR 1Gbit x32 dual die implementation • Each die is organized as 4 banks x 8 Mbit x16 • Double-data-rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is ...
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... Type Description Commercial Temperature Range 133 MHz 4 Banks × 8 Mbit × 32 Low Power DDR Mobile-RAM HYB18M1G320BF–7.5 Extended Temperature Range 133 MHz 4 Banks × 8 Mbit × 32 Low Power DDR Mobile-RAM HYE18M1G320BF–7.5 1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range) 18M: 1 ...
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Ball Configuration Rev.1.00, 2007-03 02022006-J7N7-GYFP HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM Standard ballout 1-Gbit DDR Mobile-RAM (Top View) 5 Data Sheet FIGURE 1 ...
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... Description The HY[B/E]18M1G320BF is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits internally configured as a quad-bank DRAM. The HY[B/E]18M1G320BF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls ...
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... Input Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank precharged, the bank is selected by BA0 and BA1 ...
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... Functional Description The 1-Gbit x32 DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...
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first, device core power ( ) and device IO power ( DD are driven from a single power converter output. Assert and hold CKE to a HIGH level After and are stable and CKE ...
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Register Definition 2.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a ...
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Burst Length READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE ...
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Burst Starting Column Length Address ...
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Extended Mode Register The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended ...
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... Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by Table 14) ...
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State Diagram Power Power applied On Precharge All Banks MRS EMRS WRITE PRE ACT = Active BST = Burst Terminate CKEL = Enter Power-Down CKEH = Exit Power-Down DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-Down Note: ...
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Commands Command NOP DESELECT NO OPERATION ACT ACTIVE (Select bank and row) RD READ (Select bank and column and start read burst) WR WRITE (Select bank and column and start write burst) BST BURST TERMINATE or DEEP POWER-DOWN PRE ...
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CK CK Input Parameter Clock high-level width Clock low-level width Clock cycle time Address and control input setup time Address and control input hold time Address and control input pulse width 1) All AC timing characteristics assume an input slew ...
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NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to a DDR Mobile-RAM which is selected (CS = LOW). This prevents unwanted commands from being registered during idle states. Operations already in progress are ...
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MODE REGISTER SET The Mode Register and Extended Mode Register are loaded via inputs A0 - A12 (see mode register descriptions in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and ...
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ACTIVE Before any READ or WRITE commands can be issued to a bank within the DDR Mobile-RAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command and addresses BA0, BA1 ...
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Parameter ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay These parameters account for the number of clock cycles and depend on the operating frequency, as follows: 1) no. of ...
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tACmax DQS DQ tACmin DQS Data Out from column n Burst Length = 4 in the case shown CAS Latency = 3 in the case shown All DQ are valid tAC after ...
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Parameter ACTIVE to READ or WRITE delay PRECHARGE command period 1) The output timing reference level is V DDQ Parameters and are specified for full drive strength and a reference load of 20pF. This reference load is ...
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Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the ...
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CK CK Command READ NOP Address BA,Col n CL=2 DQS DQ DQS ( Data Out from column n (or column Col n (b) = Bank A, Column n (b) Burst Length = ...
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READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command should be issued ...
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READ to WRITE Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown Command READ ...
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CK CK Command READ NOP Address BA,Col n CL=2 DQS DQ DQS Data Out from column n Cases shown are either uninterrupted burst interrupted bursts subsequent elements of ...
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WRITE WRITE bursts are initiated with a WRITE command, as shown in they apply to all write operations.The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either enabled or disabled for that ...
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CK CK Case 1: t DQSS tDQSS = min DQS t WPRES t WPRE t DS DQ, DM Case 2: t tDQSS = max DQS t WPRES DQ Data In for column n Burst Length = ...
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Parameter Write postamble Write preamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay WRITE recovery time Internal write to Read command delay PRECHARGE command period 1) DQ, DM and DQS input slew ...
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CK CK Command WRITE NOP Address BA,Col b t DQSSmin DQS DQSSmax DQS Data In to column b. 3 subsequent elements of Data In are applied in the programmed order ...
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CK CK Command WRITE NOP Address BA,Col b t DQSSmin DQS DQSSmax DQS (n) = Data In to column b (column n) 3 subsequent elements of Data In are applied in ...
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CK CK Command WRITE NOP Address BA,Col b t DQSSmax DQS (n) = Data In to column b (or column n). 3 subsequent elements of Data In are applied in the programmed order following DI b. ...
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WRITE to READ Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE t burst, (WRITE to READ) should be met as shown in WTR CK CK Command ...
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WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating t the WRITE burst, should be met as shown Command WRITE NOP Address ...
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CK CK Command WRITE NOP Address BA,Col b t DQSSmax DQS Data In to column interrupted burst shown, 2 data elements are written referenced ...
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PRECHARGE The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open rows in all banks. The bank(s) will be available for a subsequent row access a t specified time ( ) ...
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AUTO PRECHARGE Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific READ or ...
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Command PRE NOP Address A10 (AP) Pre All High Row n = Bank A, Row n 2.4.9.2 SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR Mobile-RAM, ...
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CKE Command PRE NOP ARF Address A10 (AP) Pre All High-Z DQ Enter Self Refresh Mode Timing Parameters for AUTO REFRESH and SELF REFRESH Commands Parameter AUTO REFRESH to ACTIVE/AUTO REFRESH command period PRECHARGE command period ...
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POWER-DOWN Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power- down; if power-down occurs when there is a ...
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... BURST TERMINATE command (cf are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged. The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence as for power-up initialization, including the 200µ ...
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CK CK CKE Command NOP Clock Exit Stopped Clock Stop Command ACTIVE READ (Auto-Precharge Disabled) READ (Auto-Precharge Enabled) WRITE (Auto-Precharge Disabled) WRITE (Auto-Precharge Enabled) PRECHARGE AUTO REFRESH MODE REGISTER SET 1) These parameters depend on the operating frequency; the number ...
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Function Truth Tables CKEn-1 CKEn Current State L L Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H H see Table 18 ...
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Current State CS RAS CAS Write (Auto Precharge Disabled This table applies when CKEn-1 was HIGH and CKEn is HIGH (see power-down or self refresh). 2) This table is bank-specific, ...
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Current State CS RAS CAS Any Idle Row Activating Active Precharging Read (Auto Precharge L ...
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AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state ...
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Electrical Characteristics 3.1 Operating Conditions Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operating Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those listed here may cause permanent ...
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Parameter Input capacitance: CK, CK Delta input capacitance: CK, CK Input capacitance: all other input-only balls Delta input capacitance: all other input-only balls Input/output capacitance: DQ, DQS, DM Delta input/output capacitance: DQ, DQS These values are not subject ...
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Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Address and Command Inputs (BA, BA1, CKE, CS, RAS, CAS, WE) Input high voltage Input low voltage Clock Inputs (CK, CK) DC input ...
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AC Characteristics Parameter DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input setup time DQ and DM input hold time ...
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Parameter ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Auto precharge ...
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A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system recommended to turn off the weak pull-down element during read and write bursts (DQS ...
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Operating Currents Parameter & Test Conditions Operating one bank active-precharge current CKE is HIGH HIGH between valid commands; ...
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Parameter & Test Conditions Active power-down standby current with clock stop: one bank active, CKE is LOW HIGH LOW HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active non power-down ...
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... Half Drive Strength IV Curves 30.0 20.0 10.0 PD Min 0.0 PD Max 0.0 0.5 PU Min 1.5 -10.0 PU Max -20.0 -30.0 57 Data Sheet HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM TABLE 27 Self Refresh Currents Units Note HYB18M1G320BF Typ. Max. µA 1) — — 1020 1800 640 — 560 — — 740 1560 480 — 420 — — — 580 ...
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Package Outline Rev.1.00, 2007-03 02022006-J7N7-GYFP HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM 90-ball PG-VFBGA-90-5 58 Data Sheet FIGURE 42 ...
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... List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 2 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 4 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6 Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7 DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8 Inputs Timing Parameters Table 9 Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10 Timing Parameters for ACTIVE Command Table 11 Timing Parameters for READ Command ...
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List of Illustrations Figure 1 Standard ballout 1-Gbit DDR Mobile-RAM (Top View ...
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Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ...