S-93A46A SII [Seiko Instruments Inc], S-93A46A Datasheet - Page 18
S-93A46A
Manufacturer Part Number
S-93A46A
Description
CMOS SERIAL E2PROM
Manufacturer
SII [Seiko Instruments Inc]
Datasheet
1.S-93A46A.pdf
(34 pages)
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18
CMOS SERIAL E
S-93A46A/56A/66A
Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93A46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an
erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized
erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of
clocks.
Instructions are cancelled if a clock pulse whose count other than the one specified for each write instruction
(WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous Recognition of Program Disable Instruction (EWDS) as Erase Instruction
Example of S-93A56A/66A
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
In products that do not incorporate a clock pulse monitoring circuit, FFFF is
mistakenly written to address 00h. However the S-93A56A/66A detects the
overcount and cancels the instruction without performing a write operation.
(ERASE)
Figure 17 Example of Clock Pulse Monitoring Circuit Operation
2
PROM
CS
SK
DI
1
1
1
1
1
0
0
Seiko Instruments Inc.
2
Noise pulse
0
0
3
0
0
4
0
0
0
5
0
0
6
0
0
7
0
0
8
0
0
9
0
0
10
0
0
11
Rev.2.1
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