HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 41

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) imings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD
drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
t
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 3
@ CL = 4
@ CL = 5
V
REF
Symbol
t
t
t
t
t
t
t
V
CK
CK
CK
RAS
RC
RCD
RP
stabilizes. During the period before
TT
Symbol
t
t
t
t
t
t
t
.
CK
CK
CK
RAS
RC
RCD
RP
DDR2–667C
–3
4–4–4
Min.
5
3
3
45
57
12
12
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
41
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade Definition Speed Bins for DDR2–533
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
V
REF
512-Mbit Double-Data-Rate-Two SDRAM
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
stabilizes, CKE = 0.2 x
DDR2–533B
–37F
3–3–3
Min.
3.75
3.75
3.75
45
56.25
11.25
11.25
Max.
8
8
8
70000
—
—
—
HYB18T512[40/80/16]0B[C/F]
Max.
8
8
8
70000
—
—
—
V
DDQ
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
Internet Data Sheet
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
is recognized as low.
TABLE 44
TABLE 45
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.