HYB18T512800AF QIMONDA [Qimonda AG], HYB18T512800AF Datasheet - Page 17

• Manufacturer Part Number: HYB18T512800AF
• Description: 240-Pin Fully-Buffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) applies for SMB and SPD Bus Signals.
2) applies for AMB CMOS Signal RESET.
3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications.
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2× SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
Rev. 1.2, 2006-11
03292006-GUME-ERC3
Parameter
AMB Supply Voltage
DRAM Supply Voltage
Termination Voltage
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
Parameter
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
FBD Cmd to DDR Clk out that latches Cmd
FBD Cmd to DDR Write
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
Bit Lock Interval
Frame Lock Interval
the DRAMs
Symbol
V
V
V
V
V
V
V
V
I
I
L
L
CC
DD
TT
DDSPD
IH(DC)
IL(DC)
IH(DC)
IL(DC)
Symbol
t
t
t
—
—
—
—
—
t
t
EI Propagate
EID
EI
BitLock
FrameLock
1.455
1.7
0.48 ×
3.0
2.1
—
1.0
—
–90
–5
Limit Values
Min.
V
DD
t
17
Supply Voltage Levels and DC Operating Conditions
Min.
—
—
100
—
—
—
—
—
—
—
Nom.
1.5
1.8
0.50 ×
3.3
—
—
—
—
—
—
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
V
DD
Typ.
—
—
—
8.1
TBD
5.0
1.075
2.075
—
—
Max.
1.575
1.9
0.52 ×
3.6
V
0.8
—
+0.5
+90
+5
DDSPD
Max.
4
Bitlock
—
—
—
—
—
—
119
154
V
DD
Timing Parameters
Internet Data Sheet
Unit
V
V
V
V
V
V
V
V
µΑ
µΑ
Units
clks
clks
clks
ns
ns
ns
ns
ns
frames
frames
TABLE 10
TABLE 11
Note
1)
1)
2)
1)
2)
3)
Note
2)
1)2)
3)
4)
1)
1)