HYB18T512800AF QIMONDA [Qimonda AG], HYB18T512800AF Datasheet - Page 19

• Manufacturer Part Number: HYB18T512800AF
• Description: 240-Pin Fully-Buffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

5
The following table provides an overview of the measurement conditions.
Rev. 1.2, 2006-11
03292006-GUME-ERC3
Parameter
Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
IBIST
Over all IBIST modes
DRAM Idle (0 BW)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
Current Spec. and Conditions
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HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
I
DD
Measurement Conditions
Internet Data Sheet
TABLE 13
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
CC_Idle_0
DD_Idle_0
CC_Idle_1
DD_Idle_1
CC_Active_1
DD_Active_1
CC_Active_2
DD_Active_2
CC_Training
DD_Training
CC_IBIST
DD_IBIST