W25P10 WINBOND [Winbond], W25P10 Datasheet - Page 20

• Manufacturer Part Number: W25P10
• Description: 1M-BIT, 2M-BIT AND 4M-BIT SERIAL FLASH MEMORY WITH 40MHZ SPI
• Manufacturer: WINBOND [Winbond]

W25P10, W25P20 AND W25P40
7.2.11 Chip Erase (C7h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 12.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of t
(See AC Characteristics). While the Chip Erase cycle is in
CE
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory
Protection table).
Figure 12. Chip Erase Instruction Sequence Diagram
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