ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 22

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
The unregulated Channel C can be programmed to be always
on, or it can be programmed to be on when either PSON_A
or PSON_B is on. This option is configured using Bit 4 of
Register 0xFE7B.
Software Reset
The user can reset the
GO command to Register 0xFE88 (Bit 0 for Channel A; Bit 1
for Channel B). When the GO bit is written, the power supply
for Channel A or Channel B is immediately turned off, and the
channel is restarted with a soft start after a preset delay. The
delay can be programmed to 0 ms, 500 ms, 1 sec, or 2 sec using
Bits[3:2] of Register 0xFE88.
PSON Sequencing
For both the regulated Channel A and Channel B and the
unregulated Channel C, the turn-on delay, turn-off delay,
and ramp rate can be independently configured. The register
settings can be used to set up the sequencing of the channels.
Figure 21 shows a typical sequencing diagram.
•
•
The turn-on and turn-off delays for Channel A, Channel B,
and Channel C can be set to 0 ms, 50 ms, 250 ms, or 1 sec
using Register 0xFE79, Register 0xFE7A, and Register 0xFE7B,
respectively.
The PGOOD signal of a master controller can be configured to
trigger the PSON signals of multiple slave controllers.
The
can be configured to shut down an output after another output
is shut down.
PSON_A/
PSON_B
t
DON_C
V
V
V
OUT
OUT
OUT
t
ADP1053
The turn-on delays (t
times between the activation of the PSON_A/PSON_B
pins or commands that trigger the turn-on signal and the
start of the output ramp-up.
The turn-off delays (t
times between the activation of the PSON_A/PSON_B
pins or commands that trigger the turn-off signal and the
start of the output shutdown.
DON_B
A
B
C
t
DON_A
also has fault link functionality; that is, the part
Figure 21. PSON Sequencing Diagram
t
SS_C
t
SS_B
ADP1053
DON_A
DOFF_A
t
SS_A
, t
, t
power supply by writing the
DON_B
DOFF_B
, and t
, t
DOFF_C
DON_C
) are the delay
) are the delay
t
DOFF_C
t
t
DOFF_A
DOFF_B
Rev. A | Page 22 of 84
Soft Start Ramp
For either regulated channel of the ADP1053, the VS_A/VS_B
reference voltage increases from 0 V to the regulated reference
voltage after the PSON signal is received and after the turn-on
delay. The ramp rate for the reference voltage is set in Register
0xFE2A for Channel A and Register 0xFE2B for Channel B. The
first column of Table 8 shows the possible ramp rates for the
VS_A and VS_B references.
A non-zero prebias may result in a longer turn-on delay and
shorter rise time.
Table 8. Soft Start Ramp Timing
VS_A/VS_B
Reference Ramp Rate
1 V/1.75 ms
1 V/10.5 ms
1 V/21.0 ms
1 V/40.2 ms
For the unregulated Channel C, the duty cycle can be pro-
grammed to increase or decrease at a rate set by Bits[5:4] of
Register 0xFE68. The duty cycle variation can be set to 40 ns
per one, two, four, or eight switching cycles. The soft start time
for Channel C is usually faster than the soft start time for the
regulated channels.
Two variation values are used for Channel C soft start:
where:
t
and OUT2, respectively.
t
and OUT2, respectively.
t
if these PWM outputs are assigned to Channel C.
t
if these PWM outputs are assigned to Channel C.
Both edges of a PWM signal assigned to Channel C can implement
modulation during soft start. At the initiation of soft start, a
modulated edge assigned to Channel C behaves as follows:
•
•
R1
F1
SS_C1
SS_C2
and t
and t
t
t
If the edge is configured for positive modulation, the edge
timing is the preset value plus the variation value. During
soft start, the edge moves to the left until it reaches the
preset value.
If the edge is configured for negative modulation, the edge
timing is the preset value minus the variation value. During
soft start, the edge moves to the right until it reaches the
preset value.
sets the variation for OUT1, OUT3, OUT5, and OUT7
sets the variation for OUT2, OUT4, OUT6, and OUT8
SS_C1
SS_C2
F2
R2
= |t
= |t
are the timing values for the falling edges of OUT1
are the timing values for the rising edges of OUT1
F1
F2
− t
− t
R1
R2
|
|
Channel C
Duty Cycle Ramp Rate
40 ns/1 switching cycle
40 ns/2 switching cycles
40 ns/4 switching cycles
40 ns/8 switching cycles
Data Sheet