ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 30

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
EXTERNAL FLAG INPUT (FLGI/SYNI PIN)
The FLGI/SYNI pin can be configured as a synchronization
reference or as an external flag input. When this pin is con-
figured as a flag input, an external fault signal can be sent to the
pin. This flag is Bit 0 of Register 0xFEC2. The debounce time
for this flag can be set to 0 μs or 100 μs using Register 0xFE0F.
The response to the FLAGIN flag can be programmed using
Register 0xFE06. For more information, see the Protection
Actions section and the Flag Configuration Registers section.
PROTECTION ACTIONS
The VDD_OV flag can be programmed to be ignored or to shut
down the part and restart it using Bit 5 of Register 0xFE06.
The following flags can be configured to trigger protection
actions: OVP_A, OVP_B, UVP_A, UVP_B, ACSNS, CS_OCP,
CS1_A_OCP, CS1_B_OCP, CS2_A_OCP, CS2_B_OCP, OTP1,
OTP2, FLAGIN, REVERSE_A, and REVERSE_B.
Each of these flags can be individually programmed to trigger
one of the following actions:
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•
•
•
After the condition that triggered one of these flags is resolved
and the flag is cleared, the
respond as follows:
•
•
•
The first flag with an action that causes the PWM outputs to be
disabled and a resolution that includes a soft start is recorded as
the first flag ID. For more information, see the First Flag ID
Recording section.
A reenable delay can be set for all flags; this delay is used if the
configured action for a flag is to reenable the PWM outputs
after the reenable delay. This delay can be set to 250 ms, 500 ms,
1 sec, or 2 sec using Bits[7:6] of Register 0xFE06 (see Figure 28).
No action (flag ignored).
Disable PWM outputs in Channel A.
Disable PWM outputs in Channel B.
Disable all PWM outputs.
Reenable the disabled PWM outputs immediately with no
soft start.
After the reenable delay time elapses, reenable the disabled
PWM outputs with a soft start sequence.
Keep the PWM outputs disabled; the PSON signal must be
used to reenable the PWM outputs with a soft start sequence.
— If the flag action is to disable the PWM outputs in
— If the flag action is to disable the PWM outputs in
— If the flag action is to disable all PWM outputs,
Channel A, resetting PSON_A reenables the disabled
PWM outputs.
Channel B, resetting PSON_B reenables the disabled
PWM outputs.
resetting both PSON_A and PSON_B reenables all
PWM outputs.
ADP1053
can be programmed to
Rev. A | Page 30 of 84
An additional PSON delay can be added to the reenable delay
for each channel using Bits[7:5] of Register 0xFE7B. This delay
is used to control the turn-on timing of different channels.
During the reenable delay time and the PSON delay time, the
UVP_A and UVP_B flags are blanked. The ACSNS flag can also
be programmed to be blanked using Bit 6 of Register 0xFE08.
Other flags can be individually programmed to be ignored during
the soft start (see the Flag Blanking During Soft Start section).
FLAG BLANKING DURING SOFT START
Flag blanking means that when the fault condition is met, the
corresponding flag is set but there are no related actions.
The following flags are always blanked during soft start:
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The following flags can be programmed to be blanked during
soft start using Register 0xFE07.
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Note that if a flag is blanked during soft start, it is also blanked
during the PSON delay time.
LATCHED FLAGS
The
(Register 0xFEC5 to Register 0xFEC9). Flags in a latched flag
register remain set so that intermittent faults can be detected.
Reading a latched flag register resets the flags in that register
(provided that the fault no longer exists). A PSON signal can
also reset the latched flags.
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•
FLAG
V
OUT
ADP1053
FLAGIN, OTP1, OTP2, and ACSNS flags (all channels)
UVP_A and REVERSE_A (Channel A)
UVP_B and REVERSE_B (Channel B)
CS_OCP flag (Channel C)
OVP_A, CS1_A_OCP, and CS2_A_OCP flags (Channel A)
OVP_B, CS1_B_OCP, and CS2_B_OCP flags (Channel B)
PSON_A resets the flags in Register 0xFEC5, Register
0xFEC7, Register 0xFEC8, and Register 0xFEC9.
PSON_B resets the flags in Register 0xFEC6 through
Register 0xFEC9.
also has a set of latched flag registers
Figure 28. Flag Reenable Delay
t
0
t
t
D_REENABLE
D_REENABLE
OR
+
t
D_PSON
t
1
Data Sheet