ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 50

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
MANUFACTURER-SPECIFIC EXTENDED COMMAND REGISTER DESCRIPTIONS
FLAG CONFIGURATION REGISTERS
Register 0xFE00 to Register 0xFE05 and Bits[3:0] of Register 0xFE06 are used to set the flag response and the resolution after the flag is
cleared. Bits[7:6] of Register 0xFE06 set the global flag reenable delay time.
Table 30. Register 0xFE00 to Register 0xFE06—Flag Configuration Registers
Registers
0xFE00
0xFE00
0xFE01
0xFE01
0xFE02
0xFE02
0xFE03
0xFE03
0xFE04
0xFE04
0xFE05
0xFE05
0xFE06
Table 31. Register 0xFE00 to Register 0xFE05—Flag Configuration Register Bit Descriptions
Bits
[7:6]
[5:4]
[3:2]
[1:0]
Bit Name
Flag action
Action after flag
is cleared
Flag action
Action after flag
is cleared
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[3:0]
Flag
CS1_B_OCP
CS1_A_OCP
CS2_B_OCP
CS2_A_OCP
OVP_B
OVP_A
UVP_B
UVP_A
ACSNS
CS_OCP
OTP2
OTP1
FLAGIN
R/W
R/W
R/W
R/W
R/W
Description
These bits specify the action to take when the flag is set.
Bit 7
0
0
1
1
These bits specify the action to take after the flag is cleared.
Bit 5
0
0
1
1
These bits specify the action to take when the flag is set.
Bit 3
0
0
1
1
These bits specify the action to take after the flag is cleared.
Bit 1
0
0
1
1
Other Flag Configuration Registers
0xFE71
0xFE70
0xFE19
0xFE18
0xFE27
0xFE26
0xFE29
0xFE28
0xFE78
0xFE6F
0xFE76
0xFE75
0xFE0F
Bit 6
0
1
0
1
Bit 4
0
1
0
1
Bit 2
0
1
0
1
Bit 0
0
1
0
1
Flag Action
None
Disable PWM outputs in Channel A
Disable PWM outputs in Channel B
Disable all PWM outputs (Channel A, Channel B, and Channel C)
Action After Flag Is Cleared
After the reenable delay time, the PWM outputs are reenabled using the soft
start process
The PWM outputs are reenabled immediately without a soft start
A PSON signal is needed to reenable the PWM outputs
A PSON signal is needed to reenable the PWM outputs
Flag Action
None
Disable PWM outputs in Channel A
Disable PWM outputs in Channel B
Disable all PWM outputs (Channel A, Channel B, and Channel C)
Action After Flag Is Cleared
After the reenable delay time, the PWM outputs are reenabled using the soft
start process
The PWM outputs are reenabled immediately without a soft start
A PSON signal is needed to reenable the PWM outputs
A PSON signal is needed to reenable the PWM outputs
Rev. A | Page 50 of 84
Flag Registers (Read-Only Status Registers)
0xFEC1, 0xFEC6
0xFEC0, 0xFEC5
0xFEC1, 0xFEC6
0xFEC0, 0xFEC5
0xFEC1, 0xFEC6
0xFEC0, 0xFEC5
0xFEC1, 0xFEC6
0xFEC0, 0xFEC5
0xFEC2, 0xFEC7
0xFEC2, 0xFEC7
0xFEC2, 0xFEC7
0xFEC2, 0xFEC7
0xFEC2, 0xFEC7
Data Sheet