ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 52

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
Register 0xFE08 specifies whether volt-second balance control is blanked during the soft start of the channel that is configured for volt-
second balance (Channel A or Channel C). Bit 7 of Register 0xFE72 selects the channel for volt-second balance control. Register 0xFE08
also specifies whether to disable the SR outputs (OUT3, OUT4, OUT7, and OUT8) during the soft start of their assigned channel. When
synchronous rectification is not disabled on a channel during soft start, the PWM output disable settings in Register 0xFE60 determine
whether the output is disabled.
Table 34. Register 0xFE08—Volt-Second Balance Blanking and SR Disable During Soft Start
Bits
7
6
5
4
3
2
1
0
Table 35. Register 0xFE09—PGOOD Debounce
Bits
[7:6]
[5:4]
Bit Name
Reserved
ACSNS reenable
blank
First flag ID update
Flag shutdown
timing
Volt-second balance
blanking
Channel C SR disable
Channel B SR disable
Channel A SR disable
Bit Name
PGOOD_B on
debounce
PGOOD_B off
debounce
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
This bit specifies whether the ACSNS flag is blanked during the flag reenable time.
0 = do not blank the ACSNS flag during the flag reenable time.
1 = blank the ACSNS flag during the flag reenable time.
This bit specifies whether the first flag ID is saved in the EEPROM.
0 = first flag ID is not saved in the EEPROM.
1 = first flag ID is saved in the EEPROM.
This bit specifies when the PWM outputs are shut down after a flag is triggered.
0 = PWM outputs are shut down at the end of the PWM cycle.
1 = PWM outputs are shut down immediately.
This bit specifies whether volt-second balance control is blanked during the soft start of the
channel that is enabled for volt-second balance control (Channel A or Channel C, as specified
by Bit 7 of Register 0xFE72).
0 = do not blank volt-second balance control during Channel A or Channel C soft start.
1 = blank volt-second balance control during Channel A or Channel C soft start.
This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the
soft start of Channel C, if these outputs are assigned to Channel C.
0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C.
1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C.
This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the
soft start of Channel B, if these outputs are assigned to Channel B.
0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B.
1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B.
This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the
soft start of Channel A, if these outputs are assigned to Channel A.
0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A.
1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A.
Description
These bits set the PGOOD_B on debounce time, that is, the time from when the PGOOD_B on
condition is met to when the PGOOD_B flag is set.
Bit 7
0
0
1
1
These bits set the PGOOD_B off debounce time, that is, the time from when the PGOOD_B off
condition is met to when the PGOOD_B flag is cleared.
Bit 5
0
0
1
1
Bit 4
0
1
0
1
Bit 6
0
1
0
1
Rev. A | Page 52 of 84
Typical PGOOD_B On Debounce Time
0 ms
200 ms
320 ms
600 ms
Typical PGOOD_B Off Debounce Time
0 ms
200 ms
320 ms
600 ms
Data Sheet