ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 67

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
SYNCHRONIZATION SETTING REGISTERS
If the synchronization cycle for Channel A, Channel B, or Channel C is t
t
OUT
t
switches in a totem-pole structure—the operation of the power stage may be significantly affected.
Register 0xFE66 enables PWM output edge adjustment for OUT1 to OUT8. When the appropriate bit is set in Register 0xFE66, an
adjustment of (t
complementary OUT
the dead time between the falling edge of OUT
Table 95. Register 0xFE65—OUT1 and OUT2 Shutdown in Channel C Synchronization
Bits
7
6
[5:0]
Table 96. Register 0xFE66—OUT1 Through OUT8 Dead Time Adjustment in Synchronization
Bits
7
6
5
4
3
2
1
0
SYNC
SYNC
OUT
OUT
, the on times of the PWM outputs in this channel remain the same. For example, if OUT
/2 − t
Y
is programmed for a 180°C phase shift, the difference between the falling edge of OUT
X
Y
FX
Bit Name
OUT2 shutdown
OUT1 shutdown
Reserved
Bit Name
OUT8 adjustment
OUT7 adjustment
OUT6 adjustment
OUT5 adjustment
OUT4 adjustment
OUT3 adjustment
OUT2 adjustment
OUT1 adjustment
t
0
, as shown on the left side of Figure 44. If the timing of the outputs is critical—for example, when OUT
SYNCHRONIZATION WITH NO EDGE ADJUSTMENT ON
t
S
SYNC
− t
t
FX
/2 –
SYNC
X
/ OUT
t
)/2 is made on both edges of the corresponding PWM output. It is important to enable output adjustment for the
FX
t
SYNC
Y
pairs. With output edge adjustment set on both OUT
/2
t
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYNC
t
FY
/2 –
Figure 44. PWM Output Edge Adjustment in Channel C Synchronization
t
FY
Description
Setting this bit shuts down OUT2 at the start of the OUT1 switching cycle. If OUT2 is not
assigned to Channel C, this bit must be set to 0.
Setting this bit shuts down OUT1 at the start of the OUT2 switching cycle. If OUT1 is not
assigned to Channel C, this bit must be set to 0.
Reserved.
Description
Setting this bit adjusts both edges of OUT8 by (t
Setting this bit adjusts both edges of OUT7 by (t
Setting this bit adjusts both edges of OUT6 by (t
Setting this bit adjusts both edges of OUT5 by (t
Setting this bit adjusts both edges of OUT4 by (t
Setting this bit adjusts both edges of OUT3 by (t
Setting this bit adjusts both edges of OUT2 by (t
Setting this bit adjusts both edges of OUT1 by (t
t
SYNC
X
and the rising edge of OUT
t
FX
AND
Rev. A | Page 67 of 84
t
FY
S
, and t
OUT
OUT
X
Y
Y
S
is kept the same at t
is programmed to be synchronized to the switching cycle,
t
SYNCHRONIZATION WITH EDGE ADJUSTMENT ON
0
t
FX
– (
X
t
t
and OUT
S
S
/2 –
–
t
SYNC
t
FX
S
S
S
S
S
S
S
S
− t
− t
− t
− t
− t
− t
− t
− t
)/2
X
X
t
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
and the rising edge of OUT
Y
and OUT
SYNC
(as shown on the right side of Figure 44),
S
/2 − t
)/2.
)/2.
)/2.
)/2.
)/2.
)/2.
)/2.
)/2.
t
/2
FY
– (
FX
t
t
S
S
Y
/2 –
.
–
are assigned to Channel C and
t
SYNC
t
FY
)/2
t
X
SYNC
and OUT
t
FX
AND
Y
ADP1053
changes to
Y
t
FY
drive two