ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 79

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
Table 129. Register 0xFE8A—OTW1/OTW2 Settings
Bits
7
6
[5:4]
3
2
[1:0]
FLAG REGISTERS
Register 0xFEC0 through Register 0xFEC4 are flag registers that indicate the status of the flags. Register 0xFEC5 through Register 0xFEC9
are latched flag registers. In the latched flag registers, flags are not reset when the condition disappears but remain set so that intermittent
faults can be detected. Flags in the latched flag registers are cleared only by a register read (provided that the fault no longer exists) or by
asserting PSON. It is recommended that the latched flag register be read again after the faults disappear to ensure that the register was
reset. Note that latched flag bits are clocked on a low-to-high transition only.
Table 130. Register 0xFEC0—Flag Register 1 and Register 0xFEC5—Latched Flag Register 1 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Bit Name
OTW2 flag debounce
OTW2 triggers
PGOOD_B
OTW2 threshold
OTW1 flag debounce
OTW1 triggers
PGOOD_A
OTW1 threshold
Bit Name
POWER_SUPPLY_A
PGOOD_A
CS1_A_OCP
CS2_A_OCP
UVP_A
OVP_A
LIGHTLOAD_A
VS_SET_ERR_A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Description
This bit sets the OTW2 flag debounce time.
0 = 100 ms.
1 = 0 ms.
This bit specifies whether the OTW2 flag triggers PGOOD_B.
0 = OTW2 does not trigger PGOOD_B.
1 = OTW2 triggers PGOOD_B.
These bits set the OTW2 threshold.
Bit 5
0
0
1
1
This bit sets the OTW1 flag debounce time.
0 = 100 ms.
1 = 0 ms.
This bit specifies whether the OTW1 flag triggers PGOOD_A.
0 = OTW1 does not trigger PGOOD_A.
1 = OTW1 triggers PGOOD_A.
These bits set the OTW1 threshold.
Bit 1
0
0
1
1
Description
Channel A power supply is off and the PWM outputs are disabled.
This bit stays high until PSON_A is asserted.
Power-good fault on Channel A. This flag is set when the UVP_A,
POWER_SUPPLY_A, EEPROM_CRC, or SOFTSTART_FILTER_A flag is
set. The ACSNS and OTW1 flags can also be programmed to be
included.
The voltage at CS1_A is above the 1.2 V threshold.
The voltage at CS2_A is above its threshold.
VS_A is below its threshold.
OVP_A is above its threshold.
Channel A is in light load mode (CS2_A current is below the light
load threshold).
The intended VS_A reference setting is outside the allowed range.
Bit 4
0
1
0
1
Bit 0
0
1
0
1
Rev. A | Page 79 of 84
OTW2 Threshold
3.125 mV (1 LSB) above the OTP2 threshold
6.25 mV (2 LSBs) above the OTP2 threshold
9.375 mV (3 LSBs) above the OTP2 threshold
12.5 mV (4 LSBs) above the OTP2 threshold
OTW1 Threshold
3.125 mV (1 LSB) above the OTP1 threshold
6.25 mV (2 LSBs) above the OTP1 threshold
9.375 mV (3 LSBs) above the OTP1 threshold
12.5 mV (4 LSBs) above the OTP1 threshold
Register
0xFE09,
0xFE78,
0xFE8A
0xFE00,
0xFE70
0xFE01,
0xFE18
0xFE03,
0xFE28
0xFE02,
0xFE26
0xFE1A,
0xFE69
0xFE1E,
0xFE20
Action
None
PGOOD_A pin
set low
Programmable
Programmable
Programmable
Programmable
Programmable
None
ADP1053