A8287 ALLEGRO [Allegro MicroSystems], A8287 Datasheet - Page 7

• Manufacturer Part Number: A8287
• Description: LNB Supply and Control Voltage Regulator
• Manufacturer: ALLEGRO [Allegro MicroSystems]

this feature is disabled and the device is not turned off dur-
ing an overcurrent.
Status Register. The status of the A8285/A8287 read reg-
ister can be interrogated by the system master controller via
the I
• Power Not Good (PNG). When the LNB output is enabled,
and the LNB output is below 85% of the programmed LNB
voltage, the PNG bit is set.
• Disable (DIS). Provides the status of the LNB output.
When set, this indicates that the output is disabled, either
intentionally or by a fault.
• Thermal Shutdown (TSD). When the junction tempera-
ture exceeds the maximum threshold, the thermal shutdown
bit is set, which disables the LNB output. DIS also is set.
• Overcurrent (OCP). This disables LNB output when an
overcurrent appears on the LNB output for a period greater
than the ODT (ODT must be enabled for this feature to take
effect). In addition, the DIS bit is set. Note: If an overcurrent
occurs and ODT is disabled, the A8285/A8287 will operate
in current limit indefi ninitely and the OCP bit will not be set.
Output Voltage Amplitude Selection Table
VSEL3
2
C interface. Status functions include the following:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VSEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VSEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LNB (V)
12.709
13.042
13.375
13.709
14.042
14.375
14.709
15.042
18.042
18.375
18.709
19.042
19.375
19.709
20.042
20.375
LNB Supply and Control Voltage Regulator
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
• Undervoltage Lockout (VUV). When the input voltage
(V
age bit VUV is set, disabling the output.
When V
is set, indicating that an undervoltage condition has occurred.
IRQ Flag. The IRQ fl ag is activated when any fault con-
dition occurs, including: thermal shutdown, overcurrent,
undervoltage, or the occurrence of a power-up sequence.
Note that the IRQ fl ag is not activated when either (a) the
channel is disabled (DIS), as it may have been disabled
intentionally by the master controller, or (b) if PNG is active,
as the A8285/A8287 may be starting up. Fault conditions are
stored in the status registers. Also note that the IRQ fl ag will
not activate when an overcurrent occurs and ODT is dis-
abled. In this condition, the device operates within I
When the IRQ fl ag is activated during either of the above
fault conditions, and the system master controller addresses
the A8285/A8287 with the read/write bit set to 1, then the
IRQ fl ag is reset once the A8285/A8287 acknowledges the
address. When the master controller reads the data and is
acknowledged, the status registers are updated. If the fault
is removed, the A8285/A8287 is again ready for operation
(being re-enabled via a write command). Otherwise, the
controller can keep polling the A8285/A8287 until the fault
is removed.
When V
interface will not function until the internal logic supply V
has reached its operating level. Once V
ance, the VUV bit in the status register is set and the IRQ is
activated to inform the master controller of this condition.
(The IRQ is effectively acting as a power-up fl ag.) The IRQ
is reset when the A8285/A8287 acknowledges the address.
Once the master has read the status registers, the VUV bit is
reset. The device is then ready for operation.
I
lines, SCL and SDA, to access the internal Control and
Status registers of the A8285/A8287. Data is exchanged
between a microcontroller (master) and the A8285/A8287
(slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain
output, depending on the direction of the data.
2
C Interface. This is a serial interface that uses two bus
IN
) drops below the undervoltage threshold, the undervolt-
IN
IN
, is initially applied to the A8285/A8285, the I
is initially applied to the A8285/A8285, the VUV bit
A8285/A8287
REG
is within toler-
LIM
.
2
C
REG
7