ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 72

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter0 and
Timer/Counter1
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
72
ATmega8(L)
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
The prescaler is free running (i.e., operates independently of the clock select logic of the
Timer/Counter) and it is shared by Timer/Counter1 and Timer/Counter0. Since the pres-
caler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of pres-
caling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to
the first count occurs can be from 1 to N+1 system clock cycles, where N equals the
prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A prescaler reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector. Figure 30 shows a functional equivalent block diagram of the T1/T0 synchroni-
zation and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
system clock.
The edge detector generates one clk
ative (CSn2:0 = 6) edge it detects.
Figure 30. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for
at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
CLK_I/O
clk
Tn
T1
I/O
/clk
/8, f
T0
CLK_I/O
). The T1/T0 pin is sampled once every system clock cycle by the pin syn-
D Q
LE
/64, f
Synchronization
CLK_I/O
D Q
clk
I/O
/256, or f
). The latch is transparent in the high period of the internal
CLK_I/O
CLK_I/O
T1
/clk
). Alternatively, one of four taps from the pres-
T
/1024.
0
pulse for each positive (CSn2:0 = 7) or neg-
D Q
Edge Detector
2486M–AVR–12/03
Tn_sync
(To Clock
Select Logic)