LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 266
LM3S1911-IQC20-A0
Manufacturer Part Number
LM3S1911-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S1911-IQC20-A0.pdf
(426 pages)
- Current page: 266 of 426
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Universal Asynchronous Receivers/Transmitters (UARTs)
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
266
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the
bits are cleared to 0 when reset.
The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to
the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as
follows:
ILPDVSR = SysClk / F
where F
IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used.
You must choose the divisor so that 1.42 MHz < F
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note:
RO
RO
30
14
0
0
ILPDVSR
reserved
Name
IrLPBaud16
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
is nominally 1.8432 MHz.
RO
RO
Type
27
11
R/W
0
0
RO
IrLPBaud16
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
RO
RO
24
0
8
0
reserved
IrLPBaud16
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
< 2.12 MHz, which results in a low-power
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
ILPDVSR
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
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