XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 11

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
The transmitter section comprises of an 8-bit Transmit
Shift Register (TSR) and 128 bytes of FIFO which in-
cludes a byte-wide Transmit Holding Register (THR).
TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see CLK8/16
pin description). The transmitter sends the start-bit
followed by the number of data bits, inserts the proper
parity-bit if enabled, and adds the stop-bit(s). The sta-
tus of the FIFO and TSR are reported in the Line Sta-
tus Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register pro-
viding a data interface to the host processor. The host
writes transmit data byte to the THR to be converted
The host may fill the transmit FIFO with up to 128
bytes of transmit data. The THR empty flag (LSR bit-
5) is set whenever the FIFO is empty. The THR empty
flag can generate a transmit empty interrupt (ISR bit-
Only
2.10 T
2.10.1 Transmit Holding Register (THR) - Write
2.10.3 Transmitter Operation in FIFO Mode
RANSMITTER
F
IGURE
F
IGURE
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Flow Control Characters
8. T
(EMSR Bit-7)
16X or 8X
16X or 8X
Clock
RANSMITTER
7. T
Clock
Data
Byte
RANSMITTER
3.3V AND 5V DUART WITH 128-BYTE FIFO
Data Byte
Transmit
Transmit Shift Register (TSR)
O
PERATION IN
O
PERATION IN NON
Transmit
Register
Holding
(THR)
Transmit Data Shift Register
FIFO
Transmit
FIFO
(TSR)
11
into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-
0) becomes first data bit to go out. The THR is the in-
put register to the transmit FIFO of 128 bytes when
FIFO operation is enabled by FCR bit-0. Every time a
write operation is made to the THR, the FIFO data
pointer is automatically bumped to the next sequential
data location.
The host loads transmit data to THR one character at
a time. The THR empty flag (LSR bit-5) is set when
the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit-1) when
it is enabled by IER bit-1. The TSR flag (LSR bit-6) is
set when TSR becomes completely empty.
1) when the amount of data in the FIFO falls below its
programmed trigger level. The transmit empty inter-
rupt is enabled by IER bit-1. The TSR flag (LSR bit-6)
is set when TSR/FIFO becomes empty.
AND
2.10.2 Transmitter Operation in non-FIFO Mode
-FIFO M
F
THR Interrupt (ISR bit-1)
LOW
Enabled by IER bit-1
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
C
ODE
ONTROL
M
S
B
M
ODE
TXNOFIFO1
L
S
B
T XF IF O 1