XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 20

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

See “Receiver” on page 12.
See “Transmitter” on page 11.
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive
interrupts (IER BIT-0 = 1) are enabled, the RHR inter-
rupts (see ISR bits 2 and 3) status will reflect the fol-
lowing:
A. The receive data available interrupts are issued
B. FIFO level will be reflected in the ISR register
Operation
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 R
4.2 T
4.3 I
4.3.1 IER versus Receive FIFO Interrupt Mode
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
O
O
W
NTERRUPT
RANSMIT
T
ECEIVE
NLY
NLY
RITE
ABLE
XOFF1 RD/WR
XOFF2 RD/WR
FCTR RD/WR
XON1 RD/WR
XON2 RD/WR
N
TRG
EFR
R
FC
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
H
H
OLDING
E
OLDING
RD/WR Auto CTS
W
NABLE
R
WR
RD
EAD
RITE
/
R
R
R
EGISTER
Enable
RX/TX
EGISTER
Mode
B
EGISTER
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
IT
3.3V AND 5V DUART WITH 128-BYTE FIFO
-7
Auto RTS
SCPAD
(RHR) - R
Enable
(THR) - W
Swap
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
(IER) - R
IT
-6
Enhanced Registers
Special
Select
B
Table
Char
Bit-5
Bit-5
Bit-1
Bit-5
Bit-5
Bit-5
Bit-5
Trig
RITE
IT
EAD
EAD
-5
-
-
/
20
FCR[5:4],
IER [7:4],
ISR [5:4],
MCR[7:5]
Enable
B
Table
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Bit-4
Bit-4
C. The receive data ready bit (LSR BIT-0) is set as
When FCR BIT-0 equals a logic 1 for FIFO enable; re-
setting IER bits 0-3 enables the XR16C2850 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX
B. LSR BIT-1 indicates an overrun error has oc-
C. LSR BIT 2-4 provides the type of receive data er-
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO
F. LSR BIT-7 indicates a data error in at least one
Trig
Mode Operation
IT
4.3.2 IER versus Receive/Transmit FIFO Polled
-4
S
cleared when the FIFO drops below the trigger
level.
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
FIFO.
curred and that data in the FIFO may not be valid.
rors encountered for the data byte in RHR, if any.
and TSR are empty.
character in the RX FIFO.
HADED BITS ARE ENABLED WHEN
Direction
Control
RS485
B
ware
Bit-3
Bit-3
Auto
Soft-
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
RX IR
B
Input
Bit-2
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
Inv.
IT
-2
Hyst Bit-
B
Bit-1
Bit-1
Auto
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
RTS
Cntl
IT
1
-1
Hyst Bit-
EFR B
B
ware
Bit-0
Bit-0
Auto
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
RTS
Cntl
IT
0
-0
XR16C2850
IT
-4=1
LCR=0
C
REV. 2.0.0
OMMENT
X
BF