XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 4

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

ANCILLARY SIGNALS
HDCNTL#
DSRA#
DSRB#
CTSA#
CTSB#
DTRA#
DTRB#
OP2A#
OP2B#
RTSA#
RTSB#
XTAL1
XTAL2
CDB#
CDA#
N
RIA#
RIB#
RXA
RXB
AME
40-PDIP
P
10
32
24
36
25
33
34
37
22
38
19
39
23
31
13
16
17
IN
9
-
#
44-PLCC
P
11
10
36
27
40
28
37
38
41
25
42
21
43
26
35
15
18
19
IN
-
3.3V AND 5V DUART WITH 128-BYTE FIFO
#
48-TQFP
P
33
22
38
23
34
35
39
20
40
16
41
21
32
37
13
14
IN
5
4
9
#
T
YPE
O
O
O
O
I
I
I
I
I
I
I
4
UART channel A Receive Data or infrared receive data.
Normal receive data input must idle at logic 1 condition.
The infrared receiver pulses typically idles at logic 0 but
can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used,
tie it to VCC or pull it high via a 100k ohm resistor.
UART channel A or B Request-to-Send (active low) or
general purpose output. This output must be asserted
prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6].
UART channel A or B Clear-to-Send (active low) or gen-
eral purpose input. It can be used for auto CTS flow con-
trol, see EFR[7], and IER[7]. This input should be
connected to VCC when not used.
UART channel A or B Data-Terminal-Ready (active low)
or general purpose output. If it is not used, leave it uncon-
nected.
UART channel A or B Data-Set-Ready (active low) or
general purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
UART channel A or B Carrier-Detect (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
UART channel A or B Ring-Indicator (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
Output Port 2 channel A or B - The output state is defined
by the user and through the software setting of MCR[3].
INTA or INTB is set to the active mode and OP2A# or
OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTA or INTB is set to the three state mode and OP2A#
or OP2B# to a logic 1 when MCR[3] is set to a logic 0.
See MCR[3]. This output should not be used as a general
output else it will disturb the INTA or INTB output function-
ality.
Crystal or external clock input.
Crystal or buffered clock output.
RS-485 half duplex directional control for channel A and B
(active low). Connect to VCC for normal RTS# function
and connect to GND for RS-485 half duplex direction con-
trol. RTS# pin goes low for transmit and high for receive.
This pin is wire “OR-ed” with FCTR[3]. See FCTR[3].
D
ESCRIPTION
XR16C2850
REV. 2.0.0