A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 19

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

5 4 S X F a m i l y F PG A s
G u i d e l i n e s f or C a l c u l a t i ng P ow e r
C o n s u m p t i on
The following guidelines are meant to represent worst-case
scenarios so that they can be generally used to predict the
upper limits of power dissipation. These guidelines are as
follow:
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads (q
Second Routed Array Clock Loads (q
Load Capacitance (C
Average Logic Module Switching Rate
(f
Average Input Switching Rate (f
Average Output Switching Rate (f
Average First Routed Array Clock Rate
(f
Average Second Routed Array Clock
Rate (f
Average Dedicated Array Clock Rate
(f
Dedicated Clock Array clock loads (s
S a m p l e P o w e r C a l c u l a t i o n
One of the designs used to characterize the A54SX family
was a 528 bit serial in serial out shift register. The design
utilized 100% of the dedicated flip-flops of an A54SX16P
device. A pattern of 0101… was clocked into the device at
frequencies ranging from 1 MHz to 200 MHz. Shifting in a
series of 0101… caused 50% of the flip-flops to toggle from
low to high at every clock cycle.
Follow the steps below to estimate power consumption. The
values provided for the sample calculation below are for the
shift register design above. This method for estimating
power consumption is conservative and the actual power
consumption of your design may be less than the estimated
power consumption.
The total power dissipation for the 54SX family is the sum of
the AC power dissipation and the DC power dissipation.
P
Total
m
q1
s1
)
)
)
= P
q2
)
AC
(dynamic power) + P
L
)
n
)
p
DC
1
)
)
2
1
(static power)
) = 20% of register
) = 20% of regular
= 20% of modules
= # inputs/4
= # output/4
= 20% of register
= 35 pF
= f/10
= f/5
= f/10
= f/2
= f/2
= f
cells
cells
modules
(5)
v3.1
A C P ow e r D i s s i pa t i o n
P
P
P
(n * C
Buffer
(0.5 * (q
(0.5 * (q
(0.5 * (s
Step #1: Define Terms Used in Formula
V
Module
Number of logic modules switching at f
(Used 50%)
Average logic modules switching rate
f
Module capacitance C
Input Buffer
Number of input buffers switching at f
Average input switching rate f
(Guidelines: f/5)
Input buffer capacitance C
Output Buffer
Number of output buffers switching at f
Average output buffers switching rate
f
Output buffers buffer Capacitance C
Output Load capacitance C
RCLKA
Number of Clock loads q
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
RCLKB
Number of Clock loads q
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
HCLK
Number of Clock loads
Variable capacitance of dedicated
array clock (pF)
Fixed capacitance of dedicated
array clock (pF)
Average clock rate (MHz)
m
p
CCA
AC
Output Buffer
AC
(MHz) (Guidelines: f/10)
(MHz) (Guidelines: f/10)
= P
= V
+
EQI
CCA
Module
1
1
2
* C
* f
* C
* C
2
n
* [(m * C
EQHV
+ P
)
EQCR
EQCR
Input Buffer
+ P
Input Buffer
RCLKA Net
* f
* f
* f
s1
q1
q2
EQM
) + (C
EQM
) + (r
)+ (r
+ (p * (C
1
2
* f
(pF)
EQI
L
+ P
2
1
EQHF
m
(pF)
* f
* f
n
)
(pF)
RCLKB Net
Module
q2
(MHz)
q1
EQO
))
* f
))
RCLKB
s1
RCLKA
EQO
+ C
))
+
n
m
p
HCLK
(pF) C
+ P
L
) * f
+
+
HCLK Net
]
3.3
m
f
C
n
f
C
p
f
C
q
C
f
r
q
C
f
r
s
C
C
f
p
m
n
p
q1
q2
s1
1
2
1
1
2
EQM
EQI
EQO
L
EQCR
EQCR
EQHV
EQHF
)
Output
+
264
20
4.0
1
40
3.4
1
20
4.7
35
528
1.6
200
138
0
1.6
0
138
0
0.615
96
0
(6)
(7)
19