A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 26
A54SX08-1BG208
Manufacturer Part Number
A54SX08-1BG208
Description
54SX Family FPGAs
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.A54SX08-1BG208.pdf
(57 pages)
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A 5 4 S X 0 8 T i m i n g C h ar a c te r i s t i c s
(Worst-Case Commercial Conditions)
26
Parameter
Dedicated (Hard-Wired) Array Clock Network
t
t
t
t
t
t
f
Routed Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
TTL Output Module Timing
t
t
t
t
t
t
Note:
1.
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RPWH
RPWL
RCKSW
RCKSW
RCKSW
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
Delays based on 35 pF loading, except t
Description
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
Min. Pulse Width HIGH
Min. Pulse Width LOW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
(Pad to R-Cell Input)
(Pad to R-Cell Input)
1
ENZL
and t
ENZH
. For t
(continued)
Min.
‘–3’ Speed
1.4
1.4
2.7
2.1
2.1
ENZL
v3.1
and t
Max.
350
1.0
1.0
0.1
1.3
1.4
1.4
1.5
1.5
1.5
0.1
0.3
0.3
1.6
1.6
2.1
2.3
1.4
1.3
ENZH
Min.
the loading is 5 pF.
1.6
1.6
3.1
2.4
2.4
‘–2’ Speed
Max.
320
1.1
1.2
0.2
1.5
1.6
1.7
1.7
1.7
1.8
0.2
0.3
0.3
1.9
1.9
2.4
2.7
1.7
1.5
Min.
1.8
1.8
3.6
2.7
2.7
‘–1’ Speed
Max.
280
1.3
1.4
0.2
1.7
1.8
1.9
2.0
1.9
2.0
0.2
0.4
0.4
2.1
2.1
2.8
3.1
1.9
1.7
5 4 S X F a m i l y F P G A s
Min.
‘Std’ Speed
2.1
4.2
3.2
3.2
2.1
Max.
240
0.2
2.5
3.2
3.6
1.5
1.6
2.0
2.1
2.2
2.3
2.2
2.3
0.2
0.4
0.4
2.5
2.2
2.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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