ADUM1310 AD [Analog Devices], ADUM1310 Datasheet - Page 3

• Manufacturer Part Number: ADUM1310
• Description: Triple-Channel Digital Isolator with Programmable Default Output
• Manufacturer: AD [Analog Devices]

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ V
unless otherwise noted; all typical specifications are at T
Table 1.
Parameter
DC SPECIFICATIONS
SWITCHING SPECIFICATIONS
1
2
3
4
5
6
7
8
9
Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
load within the recommended operating conditions.
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Table 9).
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for
supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4
through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for
total I
PHL
PSK
information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance
on calculating the per-channel supply current for a given data rate.
Total Supply Current, Three Channels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic High Output
Common-Mode Transient Immunity at Logic Low Output
Refresh Rate
Input Enable Time
Input Disable Time
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
H
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
V
V
V
V
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Change vs. Temperature
DD1
DD1
DD2
DD1
DD2
and I
Supply Current, Quiescent
Supply Current, Quiescent
Supply Current, 10 Mbps Data Rate
Supply Current, 10 Mbps Data Rate
DD1
DD2
≤ 5.5 V, 4.5 V ≤ V
supply currents as a function of the data rate for the ADuM1310 channel configurations.
8
4
8
3
2
5
PLH
– t
PHL
DD2
6
|
4
≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
1
DISABLE
9
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
PHL
9
and/or t
Ix
signal to the 50% level of the rising edge of the V
PLH
7
that is measured between units at the same operating temperature, supply voltages, and output
A
7
= 25°C, V
Symbol
I
I
I
I
I
I
V
V
V
V
V
V
PW
t
PWD
t
t
t
|CM
|CM
f
t
t
I
I
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
IA
ID
DDI (D)
DDO (D)
PHL
PSK
PSKCD
R
r
ENABLE
DISABLE
IH
IL
OAH
OCH
OAL
OCL
/t
, I
, I
Rev. E | Page 3 of 16
, t
F
IB
CTRL
, V
, V
H
L
, V
, V
, I
|
|
PLH
IC
ODL
OBL
, I
OBH
ODH
,
DISABLE
,
,
DD1
Ix
signal to the 50% level of the falling edge of the V
= V
Min
–10
0.8
V
10
20
25
25
DD1,
DD2
V
DD2
= 5 V; all voltages are relative to their respective ground.
− 0.4 4.8
O
> 0.8 V
Typ
2.4
1.2
6.6
2.1
+0.01 +10 μA
0.2
30
5
2.5
35
35
1.2
0.19
0.05
DD2
Ox
. CM
signal.
L
Max Unit
3.2
1.6
9.0
3.0
2.0
0.4
100 ns
50
5
30
5
2.0
5.0
is the maximum common-mode voltage slew rate
mA
mA
mA
mA
V
V
V
V
Mbps
ns
ns
ps/°C
ns
ns
ns
kV/μs
kV/μs
Mbps
μs
μs
mA/Mbps
mA/Mbps
Ox
Test Conditions
V
V
5 MHz logic signal frequency
5 MHz logic signal frequency
I
I
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
V
V
0 ≤ V
V
Ox
Ox
signal. t
IA
IA
L
L
L
L
L
L
L
L
Ix
Ix
IA
IA
DISABLE
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
, V
, V
= –4 mA, V
= +4 mA, V
= V
= 0 V, V
= V
= V
IB
IB
IA
DD1
, V
, V
IB
IB
, V
≤ V
= V
= V
PLH
IC
IC
/V
IB
, V
, V
, V
CM
propagation delay is
DD1
DD2
ADuM1310
IC
IC
ID
ID
IC
= 1000 V,
DISABLE
= V
= V
, 0 ≤ V
Ix
, V
Ix
= 0 or V
= 0 or V
, V
= V
= V
CM
ID
ID
ID
,
is set high
= 0
= 0
IxH
= 1000 V,
IxL
CTRL
DD1
DD1
≤ V
DD2