HD6412350 Hitachi, HD6412350 Datasheet - Page 157
HD6412350
Manufacturer Part Number
HD6412350
Description
(HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6412350.pdf
(989 pages)
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6.2.7
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock, and controls the refresh timer.
DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control
is not performed in normal mode.
Bit 7
RFSHE
0
1
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-
RAS refreshing.
Bit 6
RCW
0
1
Bit
Initial value
R/W
DRAM Control Register (DRAMCR)
Description
Refresh control is not performed
Refresh control is performed
Description
Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T
:
:
:
RFSHE
R/W
7
0
Rr
Rc1
cycle
cycle
RCW
R/W
6
0
RMODE
R/W
5
0
CMF
R/W
4
0
CMIE
R/W
3
0
CKS2
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0
137
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