HD6412350 Hitachi, HD6412350 Datasheet - Page 412

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

9.14.2
Table 9-25 shows the port G register configuration.
Table 9-25 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Notes: 1. Lower 16 bits of the address.
Port G Data Direction Register (PGDDR)
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes
1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
392
Bit
Modes 1, 4, 5
Initial value
R/W
Modes 2, 3, 6, 7
Initial value
R/W
Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351]
Pin PG
to 1, and as an input port when the bit is cleared to 0.
For pins PG
while clearing the bit to 0 makes the pin an input port.
2. Value of bits 4 to 0.
3. Initial value depends on the mode.
Register Configuration
4
functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set
:
:
:
:
:
3
to PG
Undefined
Undefined
—
—
—
7
0
, setting the corresponding PGDDR bit to 1 makes the pin an output port,
Undefined
Undefined
—
—
—
6
Abbreviation
PGDDR
PGDR
PORTG
Undefined
Undefined
—
—
—
5
PG4DDR
W
W
4
1
0
R/W
W
R/W
R
PG3DDR
W
W
3
0
0
Initial Value*
H'10/H'00*
H'00
Undefined
PG2DDR
W
W
2
0
0
3
PG1DDR
2
W
W
1
0
0
Address*
H'FEBF
H'FF6F
H'FF5F
PG0DDR
W
W
0
0
0
1