HD6433682 ETC, HD6433682 Datasheet - Page 362

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

19.4
19.4.1
The HD64N3687G has a multi-chip structure with two internal chips of the HD64F3687G (F-
ZTAT™ version) and 512-byte EEPROM. The HD6483687G has a multi-chip structure with two
internal chips of the HD6433687G (mask-ROM version) and 512-byte EEPROM.
The EEPROM interface is the I
communication with the external devices connected to the I
19.4.2
The I
formats specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
2.
The bus format and bus timing of the EEPROM are shown in figure 19.2.
19.4.3
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.
Rev. 3.00, 05/03, page 332 of 472
SCL
SDA
Legend: R/ : R/
upper address and lower address from each MSB side.
condition
The write data is transmitted from the MSB side.
Start
2
C bus format and the I
ACK: acknowledge
Operation
EEPROM Interface
Bus Format and Timing
Start Condition
1
code (0 is for a write and 1 is for a read),
2
Slave address
3
4
Figure 19.2 EEPROM Bus Format and Bus Timing
5
6
2
C bus timing follow section 17.4.1, I
2
7
C bus interface. This I
R/
8
ACK
9
Upper memory
A15
1
address
A8
8
ACK
9
A7
lower memory
1
2
C bus is open to the outside, so the
address
2
C bus can be made.
A0
8
ACK
9
2
C Bus Format. The bus
D7
1
Data
D0
8
ACK
9
D7
1
Data
D0
8
ACK
9
conditon
Stop