Z8F160x Zilog, Z8F160x Datasheet - Page 121
Z8F160x
Manufacturer Part Number
Z8F160x
Description
Z8 Encore / Microcontrollers with Flash Memory and 10 Bit A/D Converter
Manufacturer
Zilog
Datasheet
1.Z8F160X.pdf
(246 pages)
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PS017610-0404
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format PHASE Equals Zero
Figure 77 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to
0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set
to one. The diagram may be interpreted as either a Master or Slave timing diagram since
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
Figure 77. SPI Timing When
Transfer Format PHASE Equals One
Figure 78 illustrates the timing diagram for an SPI transfer in which PHASE is one. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL set
to 1.
MOSI
MISO
SCK
SCK
SS
Bit7
Bit7
Bit6
Bit6
PHASE
Bit5
Bit5
is 0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Serial Peripheral Interface
Bit0
Bit0
Z8 Encore!
®
103
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