ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 212

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING TABLE
(V
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescaler value and number of wait cycles inserted.
The values in the right hand two columns show the timing minimum and maximum for an external clock at 24MHz, prescaler value of zero
and zero wait states.
(1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz)
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)
TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)
P = clock prescaling value (=PRS; division factor = 1+P)
Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)
Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)
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N
10 TdDS (AS)
11 TsR/W (AS)
12 TdDSR (R/W)
13 TdDW (DSW)
14 TsD(DSW)
15 ThDS (DW)
16 TdA (DR)
17 TdAs (DS)
1
2
3
4
5
6
7
8
9
DD
TsA (AS)
ThAS (A)
TdAS (DR)
TwAS
TdAz (DS)
TwDS
TdDSR (DR)
ThDR (DS)
TdDS (A)
= 3.0 - 5.5V
Symbol
(1)
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
, T
Address Set-up Time before AS
Address Hold Time after AS
AS
AS Low Pulse Width
Address Float to DS
DS Low Pulse Width
DS
Data to DS
DS
DS
RW Set-up Time before ASN
DS
Write Data Valid to DS
Write Data Set-up before DS
Data Hold Time after DS
Address Valid to Data Valid Delay (read)
AS
A
= 0 C + 70 C, C
to Data Available (read)
to DS
to Data Valid Delay (read)
to Address Active Delay
to AS
to RW and Address Not Valid Delay
Hold Time (read)
Delay
Delay
Parameter
Load
Delay
(write)
= 50pF, f
INTCLK
= 24MHz, unless otherwise specified)
Tck x Wa+TckH-9
TckL-4
Tck x (Wd+1)+3
Tck x Wa+TckH-5
0
Tck x Wd+TckH-5
Tck x Wd+TckH+4
7
TckL+11
TckL-4
Tck x Wa+TckH-17
TckL-1
-16
Tck x Wd+TckH-16
TckL-3
Tck x (Wa+Wd+1)+TckH-7
TckL-6
Formula
Value (Note)
Min Max
-16
12
17
16
16
32
17
20
18
15
0
7
4
5
45
25
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns