COP87L89RB National Semiconductor, COP87L89RB Datasheet - Page 33

• Manufacturer Part Number: COP87L89RB
• Description: 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory/ CAN Interface/ 8-Bit A/D/ and USART
• Manufacturer: National Semiconductor

Frame Formats
The counters are modified by the device’s hardware accord-
ing to the following rules:
Special error handling for the TEC counter is performed in
the following situations:
• A stuff error occurs during arbitration, when a transmitted
• An ACK-error occurs in an error passive device and no
• If only one device is on the bus and this device transmits
A receiver detects a Bit Error
during sending an active error flag.
A receiver detects a “dominant” bit
as the first bit after sending an
error flag.
After detecting the 14th consecutive
“dominant” bit following an active
error flag or overload flag or after
detecting the 8th consecutive
“dominant” bit following a passive
error flag. After each sequence of
additional 8 consecutive “dominant”
bits.
Any other error condition (stuff,
frame, CRC, ACK).
A valid reception or transmission.
A transmitter detects a Bit Error
during sending an active error
flag.
After detecting the 14th
consecutive “dominant” bit
following an active error flag or
overload flag or after detecting
the 8th consecutive “dominant”
bit following a passive error
flag. After each sequence of
additional 8 consecutive
“dominant” bits.
Any other error condition (stuff,
frame, CRC, ACK).
A valid reception or
transmission.
“recessive” stuff bit is received as a “dorminant” bit. This
does not lead to an incrementation of the TEC.
“dominant” bits are detected while sending the passive
error flag. This does not lead to an incrementation of the
TEC.
a message, it will get no acknowledgment. This will be
detected as an error and message will be repeated.
TABLE 9. Transmit Error Counter Handling
TABLE 8. Receive Error Counter Handling
Condition
Condition
(Continued)
Increment by 8
Increment by 8
Increment by 8
Decrement by
1 if Counter is not 0
Transmit Error
Increment by 8
Increment by 8
Increment by 8
Increment by 1
Decrement by 1 if
Counter is not 0
Receive Error
Counter
Counter
33
Figure 27 shows the connection of different bus states ac-
cording to the error counters.
SYNCHRONIZATION
Every receiver starts with a “hard synchronization” on the
falling edge of the SOF bit. One bit time consists of four bit
segments: Synchronization segment, propagation segment,
phase segment 1 and phase segment 2.
A falling edge of the data signal should be in the synchroni-
zation segment. This segment has the fixed length of one
time quanta. To compensate for the various delays within a
network, the propagation segment is used. Its length is pro-
grammable from 1 to 8 time quanta. Phase segment 1 and
phase segment 2 are used to resynchronize during an active
frame. The length of these segments is from 1 to 8 time
quanta long.
Two types of synchronization are supported:
Hard synchronization is done with the falling edge on the
bus while the bus is idle, which is then interpreted as the
SOF. It restarts the internal logic.
Soft synchronization is used to lengthen or shorten the bit
time while a data or remote frame is received. Whenever a
falling edge is detected in the propagation segment or in
phase segment 1, the segment is lengthened by a specific
value, the resynchronization jump width (see Figure 29 ).
If a falling edge lies in the phase segment 2 (as shown in Fig-
ure 29 ) it is shortened by the resynchronization jump width.
Only one resynchronization is allowed during one bit time.
The sample point lies between the two phase segments and
is the point where the received data is supposed to be valid.
The transmission point lies at the end of phase segment 2 to
start a new bit time with the synchronization segment.
1. The resynchronization jump width (RJW) is automati-
2. (PS1 — BTL settings any PSC setting) The PS1 of the
When the device goes “error passive” and detects an ac-
knowledge error, the TEC counter is not incremented.
Therefore the device will not go from “error passive” to
the “bus off” state due to such a condition.
cally determined from the programmed value of PS. If a
soft resynchronization is done during phase segment 1
or the propagation segment, then RJW will either be
equal to 4 internal CAN clocks (CKI/(1 + divider) ) or the
programmed value of PS, whichever is less. PS2 will
never be shorter than 1 internal CAN clock.
BTL should always be programmed to values greater
than 1. To allow device resynchronization for positive
and negative phase errors on the bus. (if PS1 is pro-
grammed to one, a bit time could only be lengthened
and never shortened which basically disables half of the
synchronization).
FIGURE 27. CAN Bus States
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