MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 64
MC9328MX1/D
Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
1.MC9328MX1D.pdf
(96 pages)
- Current page: 64 of 96
- Download datasheet (2Mb)
Specifications
3.15 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD
module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of
FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and
the application (user programming).
64
Ref
No.
3a
3b
4a
4b
5a
5b
6a
6b
1
2
7
1.
2.
3.
C
C
C
CLK frequency at Data transfer Mode (PP)
CLK frequency at Identification Mode
Clock high time
Clock low time
Clock fall time
Clock rise time
Input hold time
Input setup time
Output hold time
Output setup time
Output delay time
L
L
L
≤
≤
≤
100 pF / 250 pF (10/30 cards)
25 pF (1 card)
250 pF (21 cards)
CMD_DAT Output
CMD_DAT Input
1
1
1
3
—10/30 cards
1
—10/30 cards
—10/30 cards
—10/30 cards
3
—10/30 cards
3
—10/30 cards
Bus Clock
—10/30 cards
3
3
—10/30 cards
Figure 47. Chip-Select Read Cycle Timing Diagram
Parameter
Table 29. SDHC Bus Timing Parameter Table
MC9328MX1 Advance Information, Rev. 4
5a
Valid Data
2
1
4a
—10/30 cards
3a
3b
6a
Valid Data
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
15/75
6/33
Min
0
0
–
–
0
1.8V +/- 0.10V
7
1
10/50 (5.00)
14/67 (6.67)
2
Max
25/5
400
16
–
–
–
–
–
–
Valid Data
Valid Data
3
3
6b
5b
10/50
10/50
4b
3.0V +/- 0.30V
Min
5/5
5/5
5/5
5/5
Freescale Semiconductor
0
0
–
–
0
10/50
10/50
Max
25/5
400
14
–
–
–
–
–
–
MHz
Unit
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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