MC9328MXL ETC, MC9328MXL Datasheet - Page 77
MC9328MXL
Manufacturer Part Number
MC9328MXL
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
1.MC9328MXL.pdf
(84 pages)
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Falling-edge latch data
3.19.2 Non-Gated Clock Mode
Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 62 on page 78 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 32 on page 78.
Freescale Semiconductor
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
VSYNC
DATA[7:0]
PIXCLK
Figure 61. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Advance Information, Rev. 5
1
2
Valid Data
3
Valid Data
4
6
5
Valid Data
Specifications
77