GAL20V8 Lattice Semiconductor, GAL20V8 Datasheet - Page 17

• Manufacturer Part Number: GAL20V8
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

Circuitry within the GAL20V8 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs set
low after a specified time (
the registered output pins (if they are enabled) will always be high
on power-up, regardless of the programmed polarity of the output
pins. This feature can greatly simplify state machine design by pro-
viding a known state on power-up. Because of the asynchronous
nature of system power-up, some conditions must be met to provide
Typ. Vref = 3.2V
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
FEEDBACK/EXTERNAL
t
pr, 1 s MAX). As a result, the state on
INTERNAL REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
Vref
Q - OUTPUT
CLK
Vcc
Vcc
Vcc (min.)
Vcc
17
t
pr
a valid power-up reset of the device. First, the V
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Typ. Vref = 3.2V
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
Tri-State
Control
t
su
Specifications GAL20V8
Feedback
t
pr time. As in normal system operation, avoid
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
CC
rise must be
PIN
PIN