SAA5500PS Philips Semiconductors, SAA5500PS Datasheet - Page 43

• Manufacturer Part Number: SAA5500PS
• Description: Standard TV Microcontrollers with On-Screen Display(OSD)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
18.1.1
The CVBS switch is used to select the required analog
input depending on the value of TXT8.CVBS1/CVBS0.
18.1.2
The output of the CVBS switch is passed to a
differential-to-single-ended converter, although in this
device it is used in single-ended configuration with a
reference. The analog output of the differential amplifier is
converted into a digital representation by a full flash ADC
with a sampling rate of 12 MHz.
18.1.3
The multi-rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from a digitised CVBS signal.
18.1.4
The data and clock standards that can be recovered are
shown in Table 11.
Table 11 Data slicing standards
18.1.5
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognises and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation. A flag
TXT12.VIDEO SIGNAL QUALITY is set when the timing
section is locked correctly to the incoming CVBS signal.
When TXT12.VIDEO SIGNAL QUALITY is set another
flag TXT12.525/625 SYNC can be used to identify the
standard.
18.1.6
The acquisition sections extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
1999 Oct 27
Standard TV microcontrollers with
On-Screen Display (OSD)
DATA STANDARD
CVBS
A
M
D
D
A
625 WST
525 WST
NALOG
CQUISITION
ATA STANDARDS
ATA
ULTI
WSS
VPS
C
-
RATE VIDEO INPUT PROCESSOR
SWITCH
APTURE TIMING
-
TO
-D
IGITAL
C
ONVERTER
CLOCK RATE
6.9375
5.7272
(MHz)
5.0
5.0
43
18.1.6.1
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR which corresponds to the number of
the page required. The bytes written into TXT3 are stored
in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
define which part of the page request is being written, and
TXT2.REQ<3:0> is used to define which of the 10 page
requests is being modified. If TXT2.REQ<3:0> is greater
than 09H, then data being written to TXT3 is ignored.
Table 12 shows the contents of the page request RAM.
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
For a 20 page device the 10 page acquisition channels are
banked, the bank being selected using TXT2.ACQ BANK.
If the ‘DO CARE’ bit for part of the page number is set to
logic 0 then that part of the page number is ignored when
the teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
‘DO CARE’ bits for the four subcode digits are all set to
logic 0 then every subcode version of the page will be
captured.
Table 12 The contents of the Page request RAM
COLUMN
START
0
1
2
3
4
5
6
7
Making a page request
DO CARE
Magazine
DO CARE
Page Tens
DO CARE
Page Units
DO CARE
Hour Tens
DO CARE
Hours
Units
DO CARE
Minutes
Tens
DO CARE
Minutes
Units
X
PRD4
HOLD MAG2 MAG1 MAG0
PT3
PU3
X
HU3
X
MU3
X
PRD3 PRD2 PRD1 PRD0
Preliminary specification
PT2
PU2
X
HU2
MT2
MU2
X
SAA55xx
PT1
PU1
HT1
HU1
MT1
MU1
E1
PT0
PU0
HT0
HU0
MT0
MU0
E0