74VHCT573ASJ Fairchild Semiconductor, 74VHCT573ASJ Datasheet
74VHCT573ASJ
Specifications of 74VHCT573ASJ
Related parts for 74VHCT573ASJ
74VHCT573ASJ Summary of contents
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... Pin and function compatible with 74HCT573 Ordering Information Package Order Number Number 74VHCT573AM M20B 74VHCT573ASJ M20D 74VHCT573AMTC MTC20 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram © ...
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... High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 Functional Description The VHCT573A contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D In this condition the latches are transparent, i ...
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... OUT 3. When outputs are in OFF-State or when GND (Outputs Active). OUT OUT CC 5. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 Parameter (4) (5) Parameter 5.0V ± 0. Rating – ...
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... Quiet Output Minimum OLV Dynamic V OL (6) V Minimum HIGH Level IHD Dynamic Input Voltage (6) V Maximum LOW Level ILD Dynamic Input Voltage Note: 6. Parameter guaranteed by design. ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 V (V) Conditions CC 4.5 5.5 4.5 5.5 4 –50µA IN ...
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... calculated by the equation Operating Requirements Symbol Parameter t (H) Minimum Pulse Width (LE Minimum Set-Up Time S t Minimum Hold Time H ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 V (V) Conditions CC 5.0 ± 0.5 C 15pF L C 50pF L 5.0 ± 0.5 C 15pF L C 50pF L 5.0 ± 0.5 R ...
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... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 Package Number M20B 6 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 Package Number M20D 7 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1997 Fairchild Semiconductor Corporation 74VHCT573A Rev. 1.3 Package Number MTC20 8 www.fairchildsemi.com ...
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