MT46V64M8FN-5B Micron Semiconductor Products, MT46V64M8FN-5B Datasheet
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MT46V64M8FN-5B
Manufacturer Part Number
MT46V64M8FN-5B
Description
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46V32M16P-5B.pdf
(83 pages)
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Table 1:
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 Banks
MT46V64M8 – 16 Meg x 8 x 4 Banks
MT46V32M16 – 8 Meg x 16 x 4 Banks
Features
• V
• V
• Bidirectional data strobe (DQS) transmitted/
• Internal, pipelined double-data-rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Auto refresh and self refresh modes
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
•
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
architecture; two data accesses per clock cycle
aligned with data for WRITEs
(x16 has two – one per byte)
t
RAS lockout supported (
-75E/-75Z
DD
DD
Speed
Grade
-5B
-75
6T
-6
= +2.5V ±0.2V, V
= +2.6V ±0.1V, V
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
CL = 2
133
133
133
133
100
DD
DD
Q = +2.5V ±0.2V
Q = +2.6V ±0.1V (DDR400)
t
RAP =
Clock Rate (MHz)
t
RCD)
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
1
Notes: 1. End of life.
Options
• Configuration
• Plastic package
• Timing – cycle time
• Self refresh
• Temperature rating
• Revision
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 66-pin TSOP
– 66-pin TSOP (Pb-free)
– 60-ball FBGA (10mm x 12.5mm)
– 60-ball FBGA (10mm x 12.5mm) (Pb-free)
– 5ns @ CL = 3 (DDR400B)
– 6ns @ CL = 2.5 (DDR333) (FBGA only)
– 6ns @ CL = 2.5 (DDR333) (TSOP only)
– 7.5ns @ CL = 2 (DDR266)
– 7.5ns @ CL = 2 (DDR266A)
– 7.5ns @ CL = 2.5 (DDR266B)
– Standard
– Low-power self refresh
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– x4, x8
– x4, x8, x16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Data-Out
Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
512Mb: x4, x8, x16 DDR SDRAM
1
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
Access
1
©2000 Micron Technology, Inc. All rights reserved.
1
DQS–DQ
Marking
+0.40ns
+0.40ns
+0.45ns
+0.50ns
+0.50ns
Features
Skew
128M4
32M16
64M8
None
None
-75E
-75Z
-5B
-6T
BN
-75
TG
FN
IT
:D
-6
:F
P
L