ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 39

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.4
The widest tolerance required for any of the given input clock frequencies is ±130 ppm for the T1 clock
(1.544 MHz). If the system clock (crystal/oscillator) accuracy is ±30 ppm, it requires a minimum pull-in range of
±160 ppm. Users who do not require the ±30 ppm freerun accuracy of the DPLL can use a ±100 ppm system clock.
Therefore the pull-in range is a minimal ±230 ppm. The pull-in range of this device is ±260 ppm.
15.0
15.1
The ZL50019 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50019
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
15.2
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is
±1023UI
15.3
The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz.
16.0
16.1
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase
detector, which represents the difference between input reference and output feedback clock. If the phase value is
below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is
done in intervals of 4 ms. The lock detector threshold and the interval are programmable by the user through the
Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See
Table 32 on page 62 and Table 33 on page 63 for the bit descriptions of the Lock Detector Threshold Register
(LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the
selected input references.
The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 36 on
page 65 for the bit description of the Reference Change Status Register (RCSR).
16.2
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In
order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and
mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during
rearrangements is less than 31 ns per rearrangement, exceeding Stratum 4E requirements. After a large number of
reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset
in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be
programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 35 on
page 63.
Pull-In/Hold-In Range (also called Locking Range)
Input Clock Cycle to Cycle Timing Variation Tolerance
Input Jitter Acceptance
Jitter Transfer Function
Lock Detector
Maximum Time Interval Error (MTIE)
p-p
Jitter Performance
DPLL Specific Functions and Requirements
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Zarlink Semiconductor Inc.
ZL50019
39
Data Sheet