SAA2521GP Philips, SAA2521GP Datasheet - Page 7

• Manufacturer Part Number: SAA2521GP
• Description: Masking threshold processor for MPEG layer 1 audio compression applications
• Manufacturer: Philips

Philips Semiconductors
Microcontroller Interface Operation
Information on the interface between microcontroller and
codec (SAA2520) will flow in a regular sequence
synchronized with the codec (SAA2520):
- with every FSYNC the SAA2521 will read the status of
- Following the calculation of the allocation and scale
- The extended settings will be sent to the codec as
The microcontroller communicates with the SAA2521 in
a similar fashion:
- status can be read continuously. The SAA2521 will
- settings can be sent following every occasion that the
- extended settings can be sent following each
August 1993
Masking threshold processor for MPEG
layer 1 audio compression applications
the codec (SAA2520)
factors the SAA2521 will send the first allocation
information unit (16-bits). It will then continuously read
the codec (SAA2520) status to ascertain when it is
able to receive further allocation information units.
When the transfer of these units is complete the
SAA2521 will send settings and (for SCALE = logic 0)
scale factor indices.
soon as possible after reception from the
microcontroller.
output a copy of the codec (SAA2520) status on the
LTDATA line except for the 'ready to receive' bits
which are generated by the SAA2521. These indicate
whether the SAA2521 is ready to receive the next
settings or extended settings.
'ready to receive' bit 'S' changes to logic 1.
occasion that the 'ready to receive' bit 'E' changes to
logic 1.
T
T
rH
sD
< 0 ns
5T
CLK24
min. set-up time FDIR to FRESET = LOW
= 210 ns (for CLK24 = 24.576 MHz) min. time FRESET HIGH
FRESET
FDIR
Fig.4 Timing: FRESET and FDIR.
t suD
t rH
7
Mode Control
Operation is controlled by the FRESET and FDIR signals.
FRESET causes a general reset. The FDIR signal is
sampled at the falling edge of the FRESET signal to
determine the operation mode:
Fig.4 shows the timing diagram for FRESET and FDIR.
Resolution Selection
The (SAA2521) is designed for operation with input
devices (ADCs) which may possess a different sample
resolution capability, i.e. audio sample inputs into the
sub-band filters. Pins RESOL0 and RESOL1 (respectively
pins 21 and 22) may be utilized to adjust the allocation
information calculation to the resolution of the samples.
With the instance of pin 20 (NODONE) being HIGH, all
available bits in the bit-pool will be allocated. If NODONE
is LOW, no bits will be allocated to the sub-bands with
energy levels below the theoretical threshold for the
selected resolution.
FDIR = logic 1
FDIR = 0
MBC123 - 1
decoding mode, SAA2521 in
feed-through mode
encoding mode, SAA2521 in
calculation mode
Preliminary specification
SAA2521