GS88132BD-150 GSI [GSI Technology], GS88132BD-150 Datasheet - Page 9
GS88132BD-150
Manufacturer Part Number
GS88132BD-150
Description
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS88132BD-150.pdf
(39 pages)
- Current page: 9 of 39
- Download datasheet (2Mb)
165-Bump BGA Pin Description
Rev: 1.05 11/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
B
ADSC, ADSP
A
Symbol
, B
A
V
ADV
TMS
TDO
MCL
DQ
DQ
DQ
DQ
LBO
TCK
V
BW
GW
TDI
V
B
0
NC
CK
ZZ
E
E
E
FT
DDQ
G
A
, B
, A
DD
SS
1
3
2
A
B
C
D
1
C
, B
D
Type
I/O
—
—
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
Address Strobe (Processor, Cache Controller); active low
9/39
Address field LSBs and Address Counter Preset Inputs
Burst address counter advance enable; active l0w
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Sleep mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
Chip Enable; active low
Scan Test Mode Select
I/O and Core Ground
Scan Test Data Out
Core power supply
Must Connect Low
Scan Test Data In
Scan Test Clock
Address Inputs
Description
No Connect
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
© 2002, GSI Technology
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