PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 15
PPC405EX-NPAFFFTX
Manufacturer Part Number
PPC405EX-NPAFFFTX
Description
PowerPC 405EX Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
1.PPC405EX-NPAFFFTX.pdf
(67 pages)
- Current page: 15 of 67
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PPC405EX – PowerPC 405EX Embedded Processor
General Purpose Timer (GPT)
The GPT provides a time base counter and system timers in addition to those defined in the processor.
Features include:
JTAG
Features include:
Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the
JTAG interface.
AMCC Proprietary
• Programmable internal/external loopback capabilities
• OPB slave (MAC) and PLB master (MAL) interfaces are 32 bits wide
• Extensive error/status vector generation for each processed packet
• VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)
• Programmable automatic source address inclusion/replacement for transmit packets
• Programmable automatic Pad/FCS stripping for receive packets
• Programmable VLAN Tag inclusion/replacement for transmit packets
• Half- or full-duplex GMII/RGMII
• Jumbo frames support
• Memory Access Layer (MAL) provides DMA capability to Ethernet channel
• Interrupt coalescence support for two transmit and two receive channels
• 32-bit time base counter driven by the OPB clock
• Seven 32-bit compare timers
• IEEE 1149.1 test access port
• JTAG Boundary Scan Description Language (BSDL)
Preliminary Data Sheet
Revision 1.09 - August 21, 2007
15
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