PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 41
PPC405EX-NPAFFFTX
Manufacturer Part Number
PPC405EX-NPAFFFTX
Description
PowerPC 405EX Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
1.PPC405EX-NPAFFFTX.pdf
(67 pages)
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PPC405EX – PowerPC 405EX Embedded Processor
Table 6. Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
AMCC Proprietary
External Peripheral Interface
PerAddr05:31
PerClk
PerCS0
PerCS1:3
PerData00:31
PerDataPar0:3
PerOE
PerReady
PerBLast
PerErr
PerRW
PerWBE0:3
ExtReset
External Bus Master Interface
BusReq
ExtAck
ExtReq
HoldReq
HoldAck
DMA Interface
DMAAck0:1
DMAAck2:3
DMAReq0:1
DMAReq2
DMAReq3
DMAEOT0:1
DMAEOT2:3
Signal Name
Address bus 5:31.
Clock output.
Chip selects 0.
Chip selects 1:3.
Data bus 0:31.
Data bus parity 0:3.
Output enable.
Slave is ready to trasfer data.
Last transfer of burst access.
External bus error.
Read/Write.
Write Byte enable 0:3.
External reset.
External bus request.
External data transfer complete.
External data transfer request.
External request for bus access.
External request acknowledge.
External peripheral DMA acknowledge.
External peripheral DMA acknowledge.
External peripheral DMA request.
External peripheral DMA request.
External peripheral DMA request.
External DMA peripheral end-of-transmission.
External DMA peripheral end-of-transmission.
Description
Preliminary Data Sheet
Revision 1.09 - August 21, 2007
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
receiver
Type
Notes
1, 2
1, 4
1, 5
1, 2
1, 2
1, 4
1, 5
1, 5
1, 5
2
2
1
1
1
1
5
5
5
41
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