PEEL18LV8ZP-25L ANACHIP [Anachip Corp], PEEL18LV8ZP-25L Datasheet - Page 8

• Manufacturer Part Number: PEEL18LV8ZP-25L
• Description: CMOS Programmable Electrically Erasable Logic Device
• Manufacturer: ANACHIP [Anachip Corp]

Table 4 - A.C. Electrical Characteristics
Over the operating range
Notes:
Anachip Corp.
www.anachip.com.tw
Symbol
1.
2.
3.
4.
5.
6.
7.
tCL, tCH
tRESET
fMAX1
fMAX2
fMAX3
tCO1
tCO2
tOD
tAW
tPD
tOE
tSC
tHC
tCP
tAR
tCF
tAP
Minimum DC input is -0.5V, however, inputs may undershoot to
-2.0V for periods less than 20 ns.
V
The Supply Voltage range of 2.7 to 3.6V was chosen to allow
this part to be used in both 3V ±10% and 3.3V ±10%
applications.
Test Points for Clock and VCC in t
the 10% and 90% levels.
I/O pins are 0V and V
"Input" refers to an input pin signal.
t
measured from input transition to V
V
OE
I
REF
and V
is measured from input transition to V
=V
Input
Input
Input
Clock to Output
Clock to comb output delay via internal registered
feedback
Clock to Feedback
Input
Input
Clock low time, clock high time
Min clock period Ext (tSC + tCO1 )
Internal feedback 1/ (tSC + tCF)
External Feedback (1/ tCP)
No Feedback 1/ (tCL + tCH)
Asynchronous Reset Pulse Width
Input to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers in clear state
O
L.
are not specified for program / verify operation.
6
6
6
6
6
to non-registered output in continuous mode
to output enable
to output disable
or feedback setup to clock
hold after clock
Registered Feedback,
Synchronous Preset
Asynchronous
Combinatorial
9
CC
Registered
Inputs I/O,
O utputs
O utputs
.
Reset
Clock
Parameter
7
7
12
R
12
OH
and t
9
-0.1V or V
12
F
REF
are referenced at
Figure 7 - Switching Waveforms
± 0.1V, T
OL
+0.1V;
14
OD
13
is
Min Max Min Max Min Max Min Max
29.4
3V±10%
20
20
40
25
25
30
8/10
0
8.
9.
10.
11.
12.
13.
14.
30
30
30
20
40
14
30
30
5
-25
Capacitances are tested on a sample basis.
Test conditions assume: signal transition times of 3ns or less
from the 10% and 90% points, timing reference levels of 1.5V
(Unless otherwise specified).
Test one output at a time for duration of less than 1 second.
I
device programmed as an 8-bit Counter.
Parameters are not 100% tested. Specifications are based on
initial characterization and are tested after any design process
modification that might affect operational frequency.
t
slower on the first transaction from sleep mode.
All inputs at GND.
3.3V±10%
41.6
33.3
38.4
CC
PD
15
13
30
25
0
for a typical application: This parameter is tested with the
, t
OE
25
25
25
15
35
25
25
, t
9
5
OD
, t
20.8
17.9
17.9
3V±10%
CO
28
28
56
40
0
, t
SC
40
40
40
28
56
20
40
40
5
, and t
I-35
3.3V±10%
29.4
25.6
27.7
AP
21
18
39
35
0
are approximately 5 ns.
35
35
35
25
49
13
35
35
5
Rev. 1.0 Dec 16, 2004
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs