LE58QL061VC Legerity, Inc., LE58QL061VC Datasheet
LE58QL061VC
Manufacturer Part Number
LE58QL061VC
Description
QFP
Manufacturer
Legerity, Inc.
Datasheet
1.LE58QL061VC.pdf
(93 pages)
Specifications of LE58QL061VC
Date_code
03+
Available stocks
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Company:
Part Number:
LE58QL061VC
Manufacturer:
LEGERITY
Quantity:
77
APPLICATIONS
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FEATURES
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ORDERING INFORMATION
Le58QL061JC
Le58QL061VC
Le58QL063VC
Codec function on telephone switch line cards
Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
Pin programmable PCM/MPI or GCI interface
Software and coefficient compatible to the Le79Q061/
063 QSLAC device
Standard PCM/microprocessor interface
(PCM/MPI mode)
— Single or Dual PCM ports available
— Time slot assigner (up to 128 channels per port)
— Clock slot and transmit clock edge options
— Optional supervision on the PCM highway
— 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,
— µP access to PCM data
— Real Time Data with interrupt (open drain or TTL)
— Broadcast mode
General Circuit Interface (GCI mode)
— Control and PCM data on a single port
— 2.048 Mbits/s data rate
— 2.048 MHz or 4.096 MHz clock option
Performs the functions of four codec/filters
Software programmable:
— SLIC device input impedance and Transhybrid balance
— Transmit and receive gains and Equalization
— Programmable Digital I/O pins with debouncing
A-law, µ-law, or linear coding
Built-in test modes with loopback, tone generation,
and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Supports multiplexed SLIC device outputs
256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
Maximum channel bandwidth for V.90 modems
Device
or 8.192 MHz master clock derived from MCLK or PCLK
44-pin PLCC
44-pin TQFP
64-pin LQFP
Quad Low Voltage Subscriber Line Audio-Processing Circuit
Package
Le58QL061/063 QLSLAC Data Sheet
RELATED LITERATURE
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DESCRIPTION
The Le58QL061/063 Quad Low Voltage Subscriber Line
Audio-Processing Circuit (QLSLAC™) devices integrate the
key functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
A dva nce d su bmi c r on CMOS t ech no log y ma kes t he
Le58QL061/063 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
The Le58QL061/063 device supports the feature set of the
Le58QL02/021/031 device and provides a General Circuit
Interface as a programmable mode.
BLOCK DIAGRAM
080753 Le58QL02/021/031 QLSLAC
080761 QSLAC™ to QLSLAC™ Design Conversion
Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
CHCLK
Analog
VOUT
VOUT
VOUT
VOUT
SLIC
VREF
CD1
CD2
CD1
CD2
CD1
CD2
CD1
CD2
VIN
VIN
VIN
VIN
C3
C4
C5
C6
C7
C3
C4
C5
C6
C7
C3
C4
C5
C6
C7
C3
C4
C5
C6
C7
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
1
1
2
2
3
3
4
4
1
1
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2
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4
4
Le58QL061/063
Signal Processing
Signal Processing
Signal Processing
Signal Processing
Channel 1 (CH 1)
Channel 2 (CH 2)
Channel 3 (CH 3)
Channel 4 (CH 4)
Interface
SLIC
(SLI)
Document ID# 080754
Rev:
Distribution:
Le58000 SLAC™Family
Reference
Circuits
Clock
&
Microprocessor Interface
D
Public Document
GCI Control Logic &
PMC & GCI Interface
Time Slot Assigner
(MPI)
(TSA)
&
™
Date:
Version: 1
QLSLAC™
Data Sheet
GCI/PCM
Interface
DXA/DU
DRA/DD
TSCA
DRB
TSCB
DIO/S1
INT
DXB
FS/FSC
PCLK/DCL
DCLK/S0
CS/PG
RST
MCLK/E1
Oct 23, 2002
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